Searched refs:REG_XDMAC_CIM21 (Results 1 – 4 of 4) sorted by relevance
333 #define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0… macro690 #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask … macro
333 #define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register 21 */ macro689 #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask … macro
333 #define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0… macro689 #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask … macro
