Searched refs:REG_XDMAC_CIM0 (Results 1 – 4 of 4) sorted by relevance
39 #define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0… macro396 #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask … macro
39 #define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register 0 */ macro395 #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask … macro
39 #define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register (chid = 0… macro395 #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask … macro
