Searched refs:REG_TWI1_IMR (Results 1 – 3 of 3) sorted by relevance
43 #define REG_TWI1_IMR (0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */ macro67 #define REG_TWI1_IMR (*(RoReg*)0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */ macro
43 #define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ macro65 #define REG_TWI1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ macro
43 #define REG_TWI1_IMR (0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ macro65 #define REG_TWI1_IMR (*(__I uint32_t*)0x4009002CU) /**< \brief (TWI1) Interrupt Mask Register */ macro
