| /hal_atmel-latest/asf/sam0/include/samd20/instance/ |
| D | tc4.h | 43 #define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */ macro
65 #define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samr21/instance/ |
| D | tc4.h | 42 #define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */ macro
64 #define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samd21/instance/ |
| D | tc4.h | 42 #define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */ macro
64 #define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samd51/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42001409) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samc20n/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42004009) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42004009UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samc20/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42004009) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42004009UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samc21/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42004009) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42004009UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samr34/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x43000809) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x43000809UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/same51/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42001409) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samc21n/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42004009) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42004009UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/same54/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42001409) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/samr35/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x43000809) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x43000809UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/saml21/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x43000809) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x43000809UL) /**< \brief (TC4) Interrupt Enable Set… macro
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| /hal_atmel-latest/asf/sam0/include/same53/instance/ |
| D | tc4.h | 40 #define REG_TC4_INTENSET (0x42001409) /**< \brief (TC4) Interrupt Enable Set */ macro
70 #define REG_TC4_INTENSET (*(RwReg8 *)0x42001409UL) /**< \brief (TC4) Interrupt Enable Set… macro
|
