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Searched refs:REG_PWM0_CPRDUPD2 (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam/include/samv71/instance/
Dpwm0.h89 #define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register (ch_num… macro
202 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Updat… macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dpwm0.h89 #define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register 2 */ macro
201 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Updat… macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dpwm0.h89 #define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register 2 */ macro
201 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Updat… macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dpwm0.h89 #define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register (ch_num… macro
201 #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Updat… macro