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Searched refs:REG_PWM0_CMPMUPD5 (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam/include/samv71/instance/
Dpwm0.h60 #define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ macro
173 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Up… macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dpwm0.h60 #define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ macro
172 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Up… macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dpwm0.h60 #define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ macro
172 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Up… macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dpwm0.h60 #define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */ macro
172 #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Up… macro