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Searched refs:REG_PWM0_CDTYUPD3 (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam/include/samv71/instance/
Dpwm0.h95 #define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch… macro
208 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle U… macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dpwm0.h95 #define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register 3 */ macro
207 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle U… macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dpwm0.h95 #define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register 3 */ macro
207 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle U… macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dpwm0.h95 #define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register (ch… macro
207 #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle U… macro