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Searched refs:REG_PWM0_CDTY3 (Results 1 – 4 of 4) sorted by relevance

/hal_atmel-latest/asf/sam/include/samv71/instance/
Dpwm0.h94 #define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = … macro
207 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle R… macro
/hal_atmel-latest/asf/sam/include/samv71b/instance/
Dpwm0.h94 #define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register 3 */ macro
206 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle R… macro
/hal_atmel-latest/asf/sam/include/same70b/instance/
Dpwm0.h94 #define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register 3 */ macro
206 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle R… macro
/hal_atmel-latest/asf/sam/include/same70/instance/
Dpwm0.h94 #define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register (ch_num = … macro
206 #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle R… macro