Home
last modified time | relevance | path

Searched refs:REG_MCLK_CPUDIV (Results 1 – 11 of 11) sorted by relevance

/hal_atmel-latest/asf/sam0/include/samc21/instance/
Dmclk.h38 #define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ macro
47 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/samc20/instance/
Dmclk.h38 #define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ macro
47 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/same53/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */ macro
50 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/samd51/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */ macro
50 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/samc20n/instance/
Dmclk.h38 #define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ macro
48 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/same51/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */ macro
50 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/samc21n/instance/
Dmclk.h38 #define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ macro
48 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/same54/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000805) /**< \brief (MCLK) CPU Clock Division */ macro
50 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000805UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/samr34/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000404) /**< \brief (MCLK) CPU Clock Division */ macro
53 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/samr35/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000404) /**< \brief (MCLK) CPU Clock Division */ macro
53 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404UL) /**< \brief (MCLK) CPU Clock Division … macro
/hal_atmel-latest/asf/sam0/include/saml21/instance/
Dmclk.h39 #define REG_MCLK_CPUDIV (0x40000404) /**< \brief (MCLK) CPU Clock Division */ macro
53 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404UL) /**< \brief (MCLK) CPU Clock Division … macro