Searched refs:REG_AFEC0_SHMR (Results 1 – 4 of 4) sorted by relevance
60 #define REG_AFEC0_SHMR (0x4003C0A0) /**< (AFEC0) AFEC Sample & Hold Mode Register */ macro93 #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< (AFEC0) AFEC Sample & Hold Mode… macro
60 #define REG_AFEC0_SHMR (0x4003C0A0) /**< (AFEC0) AFEC Sample & Hold Mode Register */ macro92 #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< (AFEC0) AFEC Sample & Hold Mode… macro
