Searched refs:uint16_t (Results 1 – 25 of 368) sorted by relevance
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46 uint16_t SWRST:1; /*!< bit: 0 Software Reset */47 uint16_t ENABLE:1; /*!< bit: 1 Enable */48 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */49 uint16_t :3; /*!< bit: 4.. 6 Reserved */50 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */51 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */52 uint16_t :3; /*!< bit: 12..14 Reserved */53 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */55 uint16_t reg; /*!< Type used for register access */112 uint16_t SWRST:1; /*!< bit: 0 Software Reset */[all …]
121 uint16_t DETACH:1; /*!< bit: 0 Detach */122 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */123 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */124 uint16_t NREPLY:1; /*!< bit: 4 No Reply */125 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */126 uint16_t TSTK:1; /*!< bit: 6 Test mode K */127 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */128 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */129 uint16_t GNAK:1; /*!< bit: 9 Global NAK */130 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */[all …]
186 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */187 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */188 uint16_t :2; /*!< bit: 2.. 3 Reserved */189 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */190 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */191 uint16_t :2; /*!< bit: 6.. 7 Reserved */192 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */193 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */194 uint16_t :2; /*!< bit: 10..11 Reserved */195 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */[all …]
136 uint16_t DETACH:1; /*!< bit: 0 Detach */137 uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */138 uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */139 uint16_t NREPLY:1; /*!< bit: 4 No Reply */140 uint16_t TSTJ:1; /*!< bit: 5 Test mode J */141 uint16_t TSTK:1; /*!< bit: 6 Test mode K */142 uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */143 uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */144 uint16_t GNAK:1; /*!< bit: 9 Global NAK */145 uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */[all …]
46 uint16_t SWRST:1; /*!< bit: 0 Software Reset */47 uint16_t ENABLE:1; /*!< bit: 1 Enable */48 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */49 uint16_t :3; /*!< bit: 4.. 6 Reserved */50 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */51 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */52 uint16_t :1; /*!< bit: 12 Reserved */53 uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */54 uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */55 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */[all …]
182 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */183 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */184 uint16_t :2; /*!< bit: 2.. 3 Reserved */185 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */186 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */187 uint16_t :2; /*!< bit: 6.. 7 Reserved */188 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */189 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */190 uint16_t :2; /*!< bit: 10..11 Reserved */191 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */[all …]
73 uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */74 uint16_t :2; /*!< bit: 10..11 Reserved */75 uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */76 uint16_t :1; /*!< bit: 15 Reserved */78 uint16_t reg; /*!< Type used for register access */113 uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */115 uint16_t reg; /*!< Type used for register access */149 uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */150 uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */151 uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */[all …]
