| /hal_atmel-3.6.0/asf/sam0/include/samd51/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/same51/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samc21/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samr34/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40001C05) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001C05UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/same54/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samc21n/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samc20/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/same53/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samc20n/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set… macro
|
| /hal_atmel-3.6.0/asf/sam0/include/saml21/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40001C05) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001C05UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samr35/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40001C05) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001C05UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samd20/instance/ |
| D | wdt.h | 39 #define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ macro
48 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samd21/instance/ |
| D | wdt.h | 38 #define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ macro
47 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set… macro
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| /hal_atmel-3.6.0/asf/sam0/include/samr21/instance/ |
| D | wdt.h | 38 #define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ macro
47 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set… macro
|
