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Searched refs:REG_TC1_RA2 (Results 1 – 8 of 8) sorted by relevance

/hal_atmel-3.5.0-3.4.0/asf/sam/include/sam4l/instance/
Dtc1.h60 #define REG_TC1_RA2 (0x40014094) /**< \brief (TC1) Register A Channel 2 */ macro
99 #define REG_TC1_RA2 (*(RwReg *)0x40014094UL) /**< \brief (TC1) Register A Channel 2… macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/sam3x/instance/
Dtc1.h61 #define REG_TC1_RA2 (0x40084094U) /**< \brief (TC1) Register A (channel = 2) */ macro
103 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40084094U) /**< \brief (TC1) Register A (channel = 2) */ macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/sam4s/instance/
Dtc1.h61 #define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ macro
103 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/same70/instance/
Dtc1.h68 #define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */ macro
118 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) … macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/sam4e/instance/
Dtc1.h66 #define REG_TC1_RA2 (0x40094094U) /**< \brief (TC1) Register A (channel = 2) */ macro
132 #define REG_TC1_RA2 (*(RwReg*)0x40094094U) /**< \brief (TC1) Register A (channel = 2) */ macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/samv71/instance/
Dtc1.h68 #define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */ macro
119 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) … macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/samv71b/instance/
Dtc1.h68 #define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */ macro
118 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) … macro
/hal_atmel-3.5.0-3.4.0/asf/sam/include/same70b/instance/
Dtc1.h68 #define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */ macro
118 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) … macro