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Searched refs:value (Results 1 – 25 of 29) sorted by relevance

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/hal_ambiq-latest/mcu/apollo4p/hal/
Dam_hal_otp.c147 uint32_t am_hal_otp_write_word(uint32_t offset, uint32_t value) in am_hal_otp_write_word() argument
165 otp_write_word_func(offset, value); in am_hal_otp_write_word()
167 if ((am_hal_load_ui32((uint32_t *)(AM_REG_OTP_BASEADDR + offset)) & value) != value) in am_hal_otp_write_word()
174 AM_REGVAL(AM_REG_OTP_BASEADDR + offset) = value; in am_hal_otp_write_word()
177 if ((AM_REGVAL(AM_REG_OTP_BASEADDR + offset) & value) != value) in am_hal_otp_write_word()
Dam_hal_adc.h578 #define AM_HAL_ADC_FIFO_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value) >> 6) argument
579 #define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value)) argument
580 #define AM_HAL_ADC_FIFO_SLOT(value) (_FLD2VAL(ADC_FIFO_SLOTNUM, value)) argument
581 #define AM_HAL_ADC_FIFO_COUNT(value) (_FLD2VAL(ADC_FIFO_COUNT, value)) argument
Dam_hal_audadc.h630 #define AM_HAL_AUDADC_FIFO_LGDATA(value) (_FLD2VAL(AUDADC_FIFOPR_LGDATAPR, value)) argument
631 #define AM_HAL_AUDADC_FIFO_HGDATA(value) (_FLD2VAL(AUDADC_FIFOPR_HGDATAPR, value)) argument
633 #define AM_HAL_AUDADC_FIFO_SLOT(value) (_FLD2VAL(AUDADC_FIFO_MIC, value)) argument
634 #define AM_HAL_AUDADC_FIFO_COUNT(value) (_FLD2VAL(AUDADC_FIFO_COUNT, value)) argument
Dam_hal_otp.h84 uint32_t am_hal_otp_write_word(uint32_t offset, uint32_t value);
Dam_hal_pdm.c639 am_hal_pdm_fifo_threshold_setup(void *pHandle, uint32_t value) in am_hal_pdm_fifo_threshold_setup() argument
649 PDMn(ui32Module)->FIFOTHR = value; in am_hal_pdm_fifo_threshold_setup()
Dam_hal_pdm.h598 uint32_t am_hal_pdm_fifo_threshold_setup(void *pHandle, uint32_t value);
/hal_ambiq-latest/mcu/apollo3p/hal/
Dam_hal_adc.h413 #define AM_HAL_ADC_FIFO_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value) >> 6) argument
414 #define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value)) argument
415 #define AM_HAL_ADC_FIFO_SLOT(value) (_FLD2VAL(ADC_FIFO_SLOTNUM, value)) argument
416 #define AM_HAL_ADC_FIFO_COUNT(value) (_FLD2VAL(ADC_FIFO_COUNT, value)) argument
Dam_hal_flash.h182 int (*flash_page_erase2_nb)( uint32_t value, uint32_t address);
197 int (*flash_info_plus_main_erase_both)( uint32_t value);
198 int (*flash_recovery)( uint32_t value);
Dam_hal_cmdq.c407 pCmdQEntry->value = pCmdQ->cmdQBufStart; in am_hal_cmdq_alloc_block()
501 pCmdQEntry->value = pCmdQ->endIdx; in am_hal_cmdq_post_block()
617 pCQAddr = (am_hal_cmdq_entry_t *)pCQAddr->value; in am_hal_cmdq_error_resume()
700 pCQAddr->value = ui32CQPauseSETCLR; in am_hal_cmdq_pause()
848 pCmdQEntry->value = 0; in am_hal_cmdq_post_loop_block()
853 pCmdQEntry->value = pCmdQ->cmdQBufStart; in am_hal_cmdq_post_loop_block()
Dam_hal_cmdq.h85 uint32_t value; member
Dam_hal_pdm.h416 uint32_t am_hal_pdm_fifo_threshold_setup(void *pHandle, uint32_t value);
Dam_hal_pdm.c439 am_hal_pdm_fifo_threshold_setup(void *pHandle, uint32_t value) in am_hal_pdm_fifo_threshold_setup() argument
449 PDMn(ui32Module)->FIFOTHR = value; in am_hal_pdm_fifo_threshold_setup()
/hal_ambiq-latest/mcu/apollo3/hal/
Dam_hal_adc.h413 #define AM_HAL_ADC_FIFO_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value) >> 6) argument
414 #define AM_HAL_ADC_FIFO_FULL_SAMPLE(value) (_FLD2VAL(ADC_FIFO_DATA, value)) argument
415 #define AM_HAL_ADC_FIFO_SLOT(value) (_FLD2VAL(ADC_FIFO_SLOTNUM, value)) argument
416 #define AM_HAL_ADC_FIFO_COUNT(value) (_FLD2VAL(ADC_FIFO_COUNT, value)) argument
Dam_hal_flash.h178 int (*flash_page_erase2_nb)( uint32_t value, uint32_t address);
193 int (*flash_info_plus_main_erase_both)( uint32_t value);
194 int (*flash_recovery)( uint32_t value);
Dam_hal_cmdq.c391 pCmdQEntry->value = pCmdQ->cmdQBufStart; in am_hal_cmdq_alloc_block()
485 pCmdQEntry->value = pCmdQ->endIdx; in am_hal_cmdq_post_block()
601 pCQAddr = (am_hal_cmdq_entry_t *)pCQAddr->value; in am_hal_cmdq_error_resume()
684 pCQAddr->value = ui32CQPauseSETCLR; in am_hal_cmdq_pause()
832 pCmdQEntry->value = 0; in am_hal_cmdq_post_loop_block()
837 pCmdQEntry->value = pCmdQ->cmdQBufStart; in am_hal_cmdq_post_loop_block()
Dam_hal_cmdq.h83 uint32_t value; member
Dam_hal_mspi.c614 *((uint32_t *)pCmd->address) = pCmd->value; in run_txn_cmdlist()
1939 pCQBlock->value = 0; in am_hal_mspi_control()
2127 pCQBlock->value = get_pause_val(pMSPIState, pCqRaw->ui32PauseCondition); in am_hal_mspi_control()
2133 pCQBlock->value = pCqRaw->pCQEntry[i].value; in am_hal_mspi_control()
2141 pCQBlock->value = AM_HAL_MSPI_PAUSE_DEFAULT; in am_hal_mspi_control()
2144 pCQBlock->value = pCqRaw->ui32StatusSetClr; in am_hal_mspi_control()
Dam_hal_iom.c1307 *((uint32_t *)pCmd->address) = pCmd->value; in run_txn_cmdlist()
3474 pCQBlock->value = 0; in am_hal_iom_control()
3666 pCQBlock->value = get_pause_val(pIOMState, pCqRaw->ui32PauseCondition); in am_hal_iom_control()
3671 pCQBlock->value = pCqRaw->pCQEntry[i].value; in am_hal_iom_control()
3679 pCQBlock->value = AM_HAL_IOM_PAUSE_DEFAULT; in am_hal_iom_control()
3682 pCQBlock->value = pCqRaw->ui32StatusSetClr; in am_hal_iom_control()
Dam_hal_pdm.h416 uint32_t am_hal_pdm_fifo_threshold_setup(void *pHandle, uint32_t value);
Dam_hal_pdm.c439 am_hal_pdm_fifo_threshold_setup(void *pHandle, uint32_t value) in am_hal_pdm_fifo_threshold_setup() argument
449 PDMn(ui32Module)->FIFOTHR = value; in am_hal_pdm_fifo_threshold_setup()
/hal_ambiq-latest/mcu/apollo4p/regs/
Dam_reg_macros.h85 #define AM_BFW(module, reg, field, value) \ argument
87 _VAL2FLD(module##_##reg##_##field, value)))
96 #define AM_BFWn(module, instance, reg, field, value) \ argument
100 _VAL2FLD(module##0_##reg##_##field, value)) )
/hal_ambiq-latest/mcu/apollo4p/hal/mcu/
Dam_hal_cmdq.c473 pCmdQEntry->value = pCmdQ->cmdQBufStart; in am_hal_cmdq_alloc_block()
558 pCmdQEntry->value = pCmdQ->endIdx; in am_hal_cmdq_post_block()
666 pCQAddr = (am_hal_cmdq_entry_t *)pCQAddr->value; in am_hal_cmdq_error_resume()
741 pCQAddr->value = ui32CQPauseSETCLR; in am_hal_cmdq_pause()
895 pCmdQEntry->value = 0; in am_hal_cmdq_post_loop_block()
903 pCmdQEntry->value = pCmdQ->cmdQBufStart; in am_hal_cmdq_post_loop_block()
Dam_hal_bootrom_helper.h96 int (*nv_recovery)( uint32_t value);
Dam_hal_cmdq.h95 uint32_t value; member
Dam_hal_iom.c3323 pCQBlock->value = 0; in am_hal_iom_control()
3517 pCQBlock->value = get_pause_val(pIOMState, pCqRaw->ui32PauseCondition); in am_hal_iom_control()
3522 pCQBlock->value = pCqRaw->pCQEntry[i].value; in am_hal_iom_control()
3530 pCQBlock->value = AM_HAL_IOM_PAUSE_DEFAULT; in am_hal_iom_control()
3533 pCQBlock->value = pCqRaw->ui32StatusSetClr; in am_hal_iom_control()

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