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Searched refs:CH (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/drivers/pwm/
Dpwm_nxp_s32_emios.c122 config->base->CH.UC[channel].C &= ~(eMIOS_C_MODE_MASK | in pwm_nxp_s32_set_cycles_opwfmb()
124 config->base->CH.UC[channel].A = pulse_cycles; in pwm_nxp_s32_set_cycles_opwfmb()
125 config->base->CH.UC[channel].B = period_cycles; in pwm_nxp_s32_set_cycles_opwfmb()
133 config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(polarity); in pwm_nxp_s32_set_cycles_opwfmb()
135 config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(!polarity); in pwm_nxp_s32_set_cycles_opwfmb()
139 config->base->CH.UC[channel].C |= eMIOS_C_MODE(EMIOS_PWM_IP_MODE_OPWFMB_FLAG); in pwm_nxp_s32_set_cycles_opwfmb()
143 config->base->CH.UC[channel].C = (config->base->CH.UC[channel].C & in pwm_nxp_s32_set_cycles_opwfmb()
153 config->base->CH.UC[channel].A = pulse_cycles; in pwm_nxp_s32_set_cycles_opwfmb()
154 config->base->CH.UC[channel].B = period_cycles; in pwm_nxp_s32_set_cycles_opwfmb()
196 config->base->CH.UC[ch_data->master_channel].C &= ~eMIOS_C_MODE_MASK; in pwm_nxp_s32_set_cycles_opwmcb()
[all …]
/Zephyr-latest/drivers/dma/
Ddma_xmc4xxx.c285 dma->CH[channel].SAR = block->source_address; in dma_xmc4xxx_config()
286 dma->CH[channel].DAR = block->dest_address; in dma_xmc4xxx_config()
287 dma->CH[channel].LLP = 0; in dma_xmc4xxx_config()
290 dma->CH[channel].CTLH = block->block_size / config->source_data_size; in dma_xmc4xxx_config()
297 dma->CH[channel].CTLL = ctll; in dma_xmc4xxx_config()
302 dma->CH[channel].LLP = (uint32_t)&descriptor_list[channel][0]; in dma_xmc4xxx_config()
303 dma->CH[channel].CTLL = BIT(GPDMA0_CH_CTLL_LLP_DST_EN_Pos) | in dma_xmc4xxx_config()
342 dma->CH[channel].CFGL = (config->channel_priority << GPDMA0_CH_CFGL_CH_PRIOR_Pos) | in dma_xmc4xxx_config()
345 dma->CH[channel].CFGH = 0; in dma_xmc4xxx_config()
385 dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_DEST_PER_Pos) | 4; in dma_xmc4xxx_config()
[all …]
Ddma_mcux_edma.c162 #define EDMA_HW_TCD_SADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
163 #define EDMA_HW_TCD_DADDR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
164 #define EDMA_HW_TCD_BITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
165 #define EDMA_HW_TCD_CITER(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
166 #define EDMA_HW_TCD_CSR(dev, ch) (DEV_BASE(dev)->CH[ch].TCD_CSR)
799 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
800 LOG_DBG("DMA CHx_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_CSR); in dma_mcux_edma_get_status()
801 LOG_DBG("DMA CHx_ES 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_ES); in dma_mcux_edma_get_status()
802 LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->CH[hw_channel].CH_INT); in dma_mcux_edma_get_status()
803 LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->CH[hw_channel].TCD_CSR); in dma_mcux_edma_get_status()
Ddma_silabs_ldma.c312 LDMA->CH[chnum].LINK & _LDMA_CH_LINK_LINK_MASK) { in dma_silabs_irq_handler()
551 if (sys_test_bit((mem_addr_t)&LDMA->CH[channel].LINK, _LDMA_CH_LINK_LINK_SHIFT)) { in silabs_ldma_append_block()
567 sys_write32((uintptr_t)desc, (mem_addr_t)&LDMA->CH[channel].LINK); in silabs_ldma_append_block()
568 sys_set_bit((mem_addr_t)&LDMA->CH[channel].LINK, _LDMA_CH_LINK_LINK_SHIFT); in silabs_ldma_append_block()
Ddma_renesas_rz.c318 p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_SETSUS_Msk; in dma_renesas_rz_suspend()
321 FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->GRP[group].CH[prv_channel].CHSTAT_b.SUS, 1); in dma_renesas_rz_suspend()
342 if (0 == p_ctrl->p_reg->GRP[group].CH[prv_channel].CHSTAT_b.SUS) { in dma_renesas_rz_resume()
348 p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL |= R_DMAC_B0_GRP_CH_CHCTRL_CLRSUS_Msk; in dma_renesas_rz_resume()
/Zephyr-latest/boards/adi/max78002evkit/doc/
Dindex.rst337 | | | | 1-2 | | | MIC ON R CH, I2S microphone data stream …
339 | | | | Open | | | MIC ON L CH, I2S microphone data stream …
/Zephyr-latest/boards/st/nucleo_wb55rg/doc/
Dnucleo_wb55rg.rst185 - PWM_2 CH 1 : PA0
/Zephyr-latest/boards/nxp/mr_canhubk3/doc/
Dindex.rst106 can_led1 Red PTE5 FXIO D7 / EMIOS1 CH5 / EMIOS0 CH 19