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Searched refs:AM_REGVAL (Results 1 – 25 of 41) sorted by relevance

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/hal_ambiq-3.7.0/mcu/apollo3p/hal/
Dam_hal_cmdq.c75 #define AM_HAL_CMDQ_ENABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) |= _VAL2FLD(IOM0_CQCFG_CQE…
76 #define AM_HAL_CMDQ_DISABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) &= ~_VAL2FLD(IOM0_CQCFG_CQ…
77 #define AM_HAL_CMDQ_INIT_CQCFG(cfgReg, pri, enable) {AM_REGVAL((cfgReg)) = _VAL2FLD(IOM0_CQCFG_CQPR…
212 hwCurIdx = AM_REGVAL(pCmdQ->pReg->regCurIdx) & AM_HAL_CMDQ_HW_IDX_MAX; in update_indices()
221 pCmdQ->cmdQHead = AM_REGVAL(pCmdQ->pReg->regCQAddr); in update_indices()
269 AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; in am_hal_cmdq_init()
270 AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; in am_hal_cmdq_init()
271 AM_REGVAL(pCmdQ->pReg->regCQPause) |= pCmdQ->pReg->bitMaskCQPauseIdx; in am_hal_cmdq_init()
273 AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCfg->pCmdQBuf; in am_hal_cmdq_init()
504 AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; in am_hal_cmdq_post_block()
[all …]
Dam_hal_flash.c656 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) in am_hal_flash_delay_status_change()
709 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) in am_hal_flash_delay_status_check()
716 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) != ui32Value ) in am_hal_flash_delay_status_check()
905 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_info_erase_disable()
951 return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_info_erase_disable_check()
1008 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & ~ui32Mask; in am_hal_flash_info_program_disable()
1062 return ((AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_info_program_disable_get()
1106 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_wipe_flash_enable()
1152 return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_wipe_flash_enable_check()
1193 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_wipe_sram_enable()
[all …]
Dam_hal_gpio.c476 ui32GPCfgVal = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgMask) >> ui32GPCfgShft; in am_hal_gpio_pinconfig_get()
477 ui32PadVal = (AM_REGVAL(ui32PadregAddr) & ui32PadMask) >> ui32PadShft; in am_hal_gpio_pinconfig_get()
478 ui32AltVal = (AM_REGVAL(ui32AltpadAddr) & ui32PadMask) >> ui32PadShft; in am_hal_gpio_pinconfig_get()
803 AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; in am_hal_gpio_pinconfig()
804 AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; in am_hal_gpio_pinconfig()
805 AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32PadClearMask) | ui32AltPadCfg; in am_hal_gpio_pinconfig()
957 ui32Regval = AM_REGVAL( AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3) ); in am_hal_gpio_state_read()
981 ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, RDA) + ui32BaseAddr); in am_hal_gpio_state_read()
985 ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32BaseAddr); in am_hal_gpio_state_read()
989 ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, ENA) + ui32BaseAddr); in am_hal_gpio_state_read()
[all …]
Dam_hal_itm.c246 while ( !AM_REGVAL(ui32StimAddr) ); in am_hal_itm_stimulus_not_busy()
270 while (!AM_REGVAL(ui32StimAddr)); in am_hal_itm_stimulus_reg_word_write()
275 AM_REGVAL(ui32StimAddr) = ui32Value; in am_hal_itm_stimulus_reg_word_write()
296 while ( !AM_REGVAL(ui32StimAddr) ); in am_hal_itm_stimulus_reg_short_write()
322 while (!AM_REGVAL(ui32StimAddr)); in am_hal_itm_stimulus_reg_byte_write()
Dam_hal_stimer.c223 AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; in am_hal_stimer_compare_delta_set()
226 cmpVal = AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); in am_hal_stimer_compare_delta_set()
269 return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); in am_hal_stimer_compare_get()
392 return AM_REGVAL(AM_REG_STIMER_NVRAM(0, ui32NvramNum)); in am_hal_stimer_nvram_get()
413 return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum)); in am_hal_stimer_capture_get()
Dam_hal_ctimer.c263 AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & in ctimer_clr()
518 AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; in am_hal_ctimer_globen()
594 AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; in am_hal_ctimer_config()
717 ui32WriteVal = AM_REGVAL(pui32ConfigReg); in am_hal_ctimer_config_single()
745 AM_REGVAL(pui32ConfigReg) = ui32WriteVal; in am_hal_ctimer_config_single()
826 ui32WriteVal = AM_REGVAL(pui32ConfigReg); in am_hal_ctimer_config_trigger()
847 AM_REGVAL(pui32ConfigReg) = ui32WriteVal; in am_hal_ctimer_config_trigger()
930 AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; in am_hal_ctimer_start()
983 AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & in am_hal_ctimer_stop()
1038 AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & in am_hal_ctimer_clear()
[all …]
Dam_hal_pwrctrl.c586 return (AM_REGVAL(AM_REG_INFO1_PATCHVER6_ADDR) & (1 << 3)) ? false : true; in simobuck_memldo_patch_check()
667 ui32RegBackupVal = AM_REGVAL(AM_REG_INFO1_TRIM22_ADDR); in am_hal_pwrctrl_bleif_workaround()
690 ui32RegBackupVal = AM_REGVAL(AM_REG_INFO1_TRIM28_ADDR); in am_hal_pwrctrl_bleif_workaround()
918 return (AM_REGVAL(0x50023870) & 0x3FF); in simobuck_vddx_default_trim_get()
922 return ((AM_REGVAL(0x50023870) >> 16) & 0x3F); in simobuck_vddx_default_trim_get()
965 return (AM_REGVAL(0x50023868) & 0x3FF); in ldo_vddx_default_trim_get()
969 return (AM_REGVAL(0x5002386C) & 0x3F); in ldo_vddx_default_trim_get()
Dam_hal_security.c190 pSecInfo->info0Version = AM_REGVAL(0x50020040); in am_hal_security_get_info()
576 uint32_t dhcsr = AM_REGVAL(0xE000EDF0); in am_hal_bootloader_exit()
587 AM_REGVAL(0xE000EDF0) = dhcsr; in am_hal_bootloader_exit()
/hal_ambiq-3.7.0/mcu/apollo3/hal/
Dam_hal_cmdq.c75 #define AM_HAL_CMDQ_ENABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) |= _VAL2FLD(IOM0_CQCFG_CQE…
76 #define AM_HAL_CMDQ_DISABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) &= ~_VAL2FLD(IOM0_CQCFG_CQ…
77 #define AM_HAL_CMDQ_INIT_CQCFG(cfgReg, pri, enable) {AM_REGVAL((cfgReg)) = _VAL2FLD(IOM0_CQCFG_CQPR…
196 hwCurIdx = AM_REGVAL(pCmdQ->pReg->regCurIdx) & AM_HAL_CMDQ_HW_IDX_MAX; in update_indices()
205 pCmdQ->cmdQHead = AM_REGVAL(pCmdQ->pReg->regCQAddr); in update_indices()
253 AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; in am_hal_cmdq_init()
254 AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; in am_hal_cmdq_init()
255 AM_REGVAL(pCmdQ->pReg->regCQPause) |= pCmdQ->pReg->bitMaskCQPauseIdx; in am_hal_cmdq_init()
257 AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCfg->pCmdQBuf; in am_hal_cmdq_init()
488 AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; in am_hal_cmdq_post_block()
[all …]
Dam_hal_gpio.c422 ui32GPCfgVal = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgMask) >> ui32GPCfgShft; in am_hal_gpio_pinconfig_get()
423 ui32PadVal = (AM_REGVAL(ui32PadregAddr) & ui32PadMask) >> ui32PadShft; in am_hal_gpio_pinconfig_get()
424 ui32AltVal = (AM_REGVAL(ui32AltpadAddr) & ui32PadMask) >> ui32PadShft; in am_hal_gpio_pinconfig_get()
731 AM_REGVAL(ui32PadregAddr) = (AM_REGVAL(ui32PadregAddr) & ui32PadClearMask) | ui32Padreg; in am_hal_gpio_pinconfig()
732 AM_REGVAL(ui32GPCfgAddr) = (AM_REGVAL(ui32GPCfgAddr) & ui32GPCfgClearMask) | ui32GPCfg; in am_hal_gpio_pinconfig()
733 AM_REGVAL(ui32AltpadAddr) = (AM_REGVAL(ui32AltpadAddr) & ui32PadClearMask) | ui32AltPadCfg; in am_hal_gpio_pinconfig()
875 ui32Regval = AM_REGVAL( AM_REGADDR(GPIO, PADREGA) + (ui32Pin & ~0x3) ); in am_hal_gpio_state_read()
899 ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, RDA) + ui32BaseAddr); in am_hal_gpio_state_read()
903 ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, WTA) + ui32BaseAddr); in am_hal_gpio_state_read()
907 ui32ReadValue = AM_REGVAL(AM_REGADDR(GPIO, ENA) + ui32BaseAddr); in am_hal_gpio_state_read()
[all …]
Dam_hal_flash.c660 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) in am_hal_flash_delay_status_change()
713 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) in am_hal_flash_delay_status_check()
720 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) != ui32Value ) in am_hal_flash_delay_status_check()
909 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_info_erase_disable()
955 return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_info_erase_disable_check()
1012 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & ~ui32Mask; in am_hal_flash_info_program_disable()
1066 return ((AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_info_program_disable_get()
1110 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_wipe_flash_enable()
1156 return AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_wipe_flash_enable_check()
1197 ui32SecurityValue = AM_REGVAL(AM_HAL_FLASH_INFO_SECURITY_ADDR) & in am_hal_flash_wipe_sram_enable()
[all …]
Dam_hal_itm.c246 while ( !AM_REGVAL(ui32StimAddr) ); in am_hal_itm_stimulus_not_busy()
270 while (!AM_REGVAL(ui32StimAddr)); in am_hal_itm_stimulus_reg_word_write()
275 AM_REGVAL(ui32StimAddr) = ui32Value; in am_hal_itm_stimulus_reg_word_write()
296 while ( !AM_REGVAL(ui32StimAddr) ); in am_hal_itm_stimulus_reg_short_write()
322 while (!AM_REGVAL(ui32StimAddr)); in am_hal_itm_stimulus_reg_byte_write()
Dam_hal_stimer.c221 AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; in am_hal_stimer_compare_delta_set()
224 cmpVal = AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); in am_hal_stimer_compare_delta_set()
262 return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); in am_hal_stimer_compare_get()
385 return AM_REGVAL(AM_REG_STIMER_NVRAM(0, ui32NvramNum)); in am_hal_stimer_nvram_get()
406 return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum)); in am_hal_stimer_capture_get()
Dam_hal_ctimer.c237 AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & in ctimer_clr()
492 AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; in am_hal_ctimer_globen()
568 AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; in am_hal_ctimer_config()
691 ui32WriteVal = AM_REGVAL(pui32ConfigReg); in am_hal_ctimer_config_single()
719 AM_REGVAL(pui32ConfigReg) = ui32WriteVal; in am_hal_ctimer_config_single()
800 ui32WriteVal = AM_REGVAL(pui32ConfigReg); in am_hal_ctimer_config_trigger()
821 AM_REGVAL(pui32ConfigReg) = ui32WriteVal; in am_hal_ctimer_config_trigger()
904 AM_REGVAL(pui32ConfigReg) = ui32ConfigVal; in am_hal_ctimer_start()
957 AM_REGVAL(pui32ConfigReg) &= ~(ui32TimerSegment & in am_hal_ctimer_stop()
1012 AM_REGVAL(pui32ConfigReg) |= (ui32TimerSegment & in am_hal_ctimer_clear()
[all …]
Dam_hal_security.c209 pSecInfo->info0Version = AM_REGVAL(0x50020040); in am_hal_security_get_info()
635 uint32_t dhcsr = AM_REGVAL(0xE000EDF0); in am_hal_bootloader_exit()
646 AM_REGVAL(0xE000EDF0) = dhcsr; in am_hal_bootloader_exit()
/hal_ambiq-3.7.0/mcu/apollo4p/hal/mcu/
Dam_hal_cmdq.c71 #define AM_HAL_CMDQ_ENABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) |= _VAL2FLD(IOM0_CQCFG_CQE…
72 #define AM_HAL_CMDQ_DISABLE_CQ(cfgReg) {AM_REGVAL((cfgReg)) &= ~_VAL2FLD(IOM0_CQCFG_CQ…
73 #define AM_HAL_CMDQ_INIT_CQCFG(cfgReg, pri, enable) {AM_REGVAL((cfgReg)) = _VAL2FLD(IOM0_CQCFG_CQPR…
289 hwCurIdx = AM_REGVAL(pCmdQ->pReg->regCurIdx) & AM_HAL_CMDQ_HW_IDX_MAX; in update_indices()
298 pCmdQ->cmdQHead = AM_REGVAL(pCmdQ->pReg->regCQAddr); in update_indices()
345 AM_REGVAL(pCmdQ->pReg->regCurIdx) = 0; in am_hal_cmdq_init()
346 AM_REGVAL(pCmdQ->pReg->regEndIdx) = 0; in am_hal_cmdq_init()
347 AM_REGVAL(pCmdQ->pReg->regCQPause) |= pCmdQ->pReg->bitMaskCQPauseIdx; in am_hal_cmdq_init()
349 AM_REGVAL(pCmdQ->pReg->regCQAddr) = (uint32_t)pCfg->pCmdQBuf; in am_hal_cmdq_init()
567 AM_REGVAL(pCmdQ->pReg->regEndIdx) = pCmdQ->endIdx & AM_HAL_CMDQ_HW_IDX_MAX; in am_hal_cmdq_post_block()
[all …]
Dam_hal_itm.c208 while ( !AM_REGVAL(ui32StimAddr) ); in am_hal_itm_stimulus_not_busy()
226 while (!AM_REGVAL(ui32StimAddr)); in am_hal_itm_stimulus_reg_word_write()
231 AM_REGVAL(ui32StimAddr) = ui32Value; in am_hal_itm_stimulus_reg_word_write()
247 while ( !AM_REGVAL(ui32StimAddr) ); in am_hal_itm_stimulus_reg_short_write()
268 while (!AM_REGVAL(ui32StimAddr)); in am_hal_itm_stimulus_reg_byte_write()
Dam_hal_utils.c151 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) in am_hal_delay_us_status_change()
191 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value ) in am_hal_delay_us_status_check()
198 if ( ( AM_REGVAL(ui32Address) & ui32Mask ) != ui32Value ) in am_hal_delay_us_status_check()
/hal_ambiq-3.7.0/mcu/apollo4p/hal/
Dam_hal_stimer.c295 AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta; in am_hal_stimer_compare_delta_set()
340 return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)); in am_hal_stimer_compare_get()
467 AM_REGVAL(AM_REG_STIMER_NVRAM(0, ui32NvramNum)) = ui32NvramVal; in am_hal_stimer_nvram_set()
486 return AM_REGVAL(AM_REG_STIMER_NVRAM(0, ui32NvramNum)); in am_hal_stimer_nvram_get()
505 return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum)); in am_hal_stimer_capture_get()
Dam_hal_otp.c111 *pVal = AM_REGVAL(AM_REG_OTP_BASEADDR + offset); in am_hal_otp_read_word()
174 AM_REGVAL(AM_REG_OTP_BASEADDR + offset) = value; in am_hal_otp_write_word()
177 if ((AM_REGVAL(AM_REG_OTP_BASEADDR + offset) & value) != value) in am_hal_otp_write_word()
Dam_hal_gpio.c432 AM_REGVAL(ui32RegAddr) &= ~ui32Msk; // Write MCUNxINTxEN in am_hal_gpio_interrupt_control()
436 AM_REGVAL(ui32RegAddr) &= ~ui32Msk; // Write MCUN1INTxEN in am_hal_gpio_interrupt_control()
441 AM_REGVAL(ui32RegAddr) |= ui32Msk; // Write MCUNnINTxEN in am_hal_gpio_interrupt_control()
445 AM_REGVAL(ui32RegAddr) |= ui32Msk; // Write MCUN1INTxEN in am_hal_gpio_interrupt_control()
669 *pui32IntStatus = bEnabledOnly ? AM_REGVAL(ui32EnblAddr) : 0xFFFFFFFF; in am_hal_gpio_interrupt_irq_status_get()
674 *pui32IntStatus &= AM_REGVAL(ui32StatAddr); in am_hal_gpio_interrupt_irq_status_get()
713 AM_REGVAL(ui32RegAddr) = ui32GpioIntMaskStatus; in am_hal_gpio_interrupt_irq_clear()
Dam_hal_pwrctrl.c797 ui32Val |= (AM_REGVAL((uint32_t)pAddr) & ~ui32Mask); in am_hal_util_write_and_wait()
1828 if ( AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & pwr_ctrl.ui32PeriphEnable ) in am_hal_pwrctrl_periph_enable()
1853 AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) |= in am_hal_pwrctrl_periph_enable()
1905 if ( (AM_REGVAL(pwr_ctrl.ui32PwrStatReqAddr) & in am_hal_pwrctrl_periph_enable()
1942 if (((AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & PWRCTRL_HCPA_DEVPWREN_MASK) != 0) && in pwrctrl_periph_disable_msk_check()
1943 ((AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & pwr_ctrl.ui32PeriphEnable) == 0)) in pwrctrl_periph_disable_msk_check()
1950 if (((AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & PWRCTRL_HCPB_DEVPWREN_MASK) != 0) && in pwrctrl_periph_disable_msk_check()
1951 ((AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & pwr_ctrl.ui32PeriphEnable) == 0)) in pwrctrl_periph_disable_msk_check()
1958 if (((AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & PWRCTRL_HCPC_DEVPWREN_MASK) != 0) && in pwrctrl_periph_disable_msk_check()
1959 ((AM_REGVAL(pwr_ctrl.ui32PwrEnRegAddr) & pwr_ctrl.ui32PeriphEnable) == 0)) in pwrctrl_periph_disable_msk_check()
[all …]
Dam_hal_dcu.c115 AM_REGVAL((pDst + numWords)) = AM_REGVAL((pSrc + numWords)); in copy_words()
Dam_hal_sysctrl.h86 #define am_hal_sysctrl_sysbus_write_flush() AM_REGVAL(SYNC_READ)
/hal_ambiq-3.7.0/utils/
Dam_util_faultisr.c93 #define AM_REGVAL(x) (*((volatile uint32_t *)(x))) macro
357 sFaultData.u32CFSR = AM_REGVAL(AM_REG_SYSCTRL_CFSR_O); in am_util_faultisr_collect_data()
366 sFaultData.u32BFAR = AM_REGVAL(AM_REG_SYSCTRL_BFAR_O); in am_util_faultisr_collect_data()

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