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27 
28 #ifndef ALTERA_MSGDMA_RESPONSE_REGS_H_
29 #define ALTERA_MSGDMA_RESPONSE_REGS_H_
30 
31 #include "io.h"
32 
33 /*
34   The response slave port only carries the actual bytes transferred,
35   error, and early termination bits.  Reading from the upper most byte
36   of the 2nd register pops the response FIFO.  For proper FIFO popping
37   always read the actual bytes transferred followed by the error and early
38   termination bits using 'little endian' accesses.  If a big endian
39   master accesses the response slave port make sure that address 0x7 is the
40   last byte lane access as it's the one that pops the reponse FIFO.
41 
42   If you use a pre-fetching descriptor master in front of the dispatcher
43   port then you do not need to access this response slave port.
44 */
45 
46 
47 
48 #define ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG    0x0
49 #define ALTERA_MSGDMA_RESPONSE_ERRORS_REG                      0x4
50 
51 /* bits making up the "errors" register */
52 #define ALTERA_MSGDMA_RESPONSE_ERROR_MASK                      0xFF
53 #define ALTERA_MSGDMA_RESPONSE_ERROR_OFFSET                    0
54 #define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_MASK          (1 << 8)
55 #define ALTERA_MSGDMA_RESPONSE_EARLY_TERMINATION_OFFSET        8
56 
57 
58 /* read macros for each 32 bit register */
59 #define IORD_ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED(base)  \
60         IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ACTUAL_BYTES_TRANSFERRED_REG)
61 /* this read pops the response FIFO */
62 #define IORD_ALTERA_MSGDMA_RESPONSE_ERRORS_REG(base)  \
63         IORD_32DIRECT(base, ALTERA_MSGDMA_RESPONSE_ERRORS_REG)
64 
65 
66 #endif /*ALTERA_MSGDMA_RESPONSE_REGS_H_*/
67