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Searched refs:clk_ctrl (Results 1 – 11 of 11) sorted by relevance

/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SYS/
Dsys_me11.c148 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_SYS_RTCClockEnable()
155 if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) != MXC_S_GCR_CLK_CTRL_CLKSEL_HFXIN) { in MXC_SYS_RTCClockDisable()
156 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_SYS_RTCClockDisable()
168 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC_EN; in MXC_SYS_ClockSourceEnable()
173 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_SYS_ClockSourceEnable()
193 current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; in MXC_SYS_ClockSourceDisable()
202 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC_EN; in MXC_SYS_ClockSourceDisable()
206 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_SYS_ClockSourceDisable()
227 if (MXC_GCR->clk_ctrl & ready) { in MXC_SYS_Clock_Timeout()
242 current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; in MXC_SYS_Clock_Select()
[all …]
Dsys_me10.c100 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_SYS_RTCClockEnable()
114 MXC_GCR->clk_ctrl &= (~MXC_F_GCR_CLK_CTRL_X32K_EN); in MXC_SYS_RTCClockDisable()
127 current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_SYSOSC_SEL; in MXC_SYS_ClockSourceDisable()
136 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_CRYPTO_EN; in MXC_SYS_ClockSourceDisable()
141 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC96_EN; in MXC_SYS_ClockSourceDisable()
144 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_HIRC8_EN; in MXC_SYS_ClockSourceDisable()
147 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_SYS_ClockSourceDisable()
165 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_CRYPTO_EN; in MXC_SYS_ClockSourceEnable()
170 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN; in MXC_SYS_ClockSourceEnable()
173 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC8_EN; in MXC_SYS_ClockSourceEnable()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/LP/
Dlp_me10.c591 if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_SYSOSC_SEL) == in MXC_LP_EnterBackgroundMode()
593 if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE) == in MXC_LP_EnterBackgroundMode()
596 MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE, in MXC_LP_EnterBackgroundMode()
619 MXC_SETFIELD(MXC_GCR->clk_ctrl, MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE, in MXC_LP_EnterBackgroundMode()
658 if ((MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CRYPTO_EN) == 0) { in MXC_LP_EnterDeepSleepMode()
660 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_CRYPTO_EN; in MXC_LP_EnterDeepSleepMode()
680 MXC_GCR->clk_ctrl &= ~MXC_F_GCR_CLK_CTRL_CRYPTO_EN; in MXC_LP_EnterDeepSleepMode()
Dlp_me11.c212 current_clock = MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL; in MXC_LP_SetOperatingVoltage()
248 div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; in MXC_LP_SetOperatingVoltage()
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/
Dsystem_max32660.c59 clk_src = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL); in SystemCoreClockUpdate()
81 div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS; in SystemCoreClockUpdate()
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/
Dsystem_max32650.c56 clk_src = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_SYSOSC_SEL); in SystemCoreClockUpdate()
78 div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_SYSCLK_PRESCALE) >> in SystemCoreClockUpdate()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/TPU/
Dtpu_me10.c34 if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CRYPTO_EN)) { in MXC_TPU_Init()
35 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_CRYPTO_EN; in MXC_TPU_Init()
37 while (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CRYPTO_RDY)) {} in MXC_TPU_Init()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/RTC/
Drtc_me11.c66 MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_X32K_EN; in MXC_RTC_Init()
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Include/
Dgcr_regs.h79 __IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */ member
/hal_adi-latest/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Include/
Dclcd_regs.h77 __IO uint32_t clk_ctrl; /**< <tt>\b 0x000:</tt> CLCD CLK_CTRL Register */ member
Dgcr_regs.h79 __IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */ member