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Searched refs:advConfig (Results 1 – 25 of 36) sorted by relevance

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/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/I2S/
Di2s_reva.c592 mxc_dma_adv_config_t advConfig; in MXC_I2S_RevA_TXDMAConfig() local
612 advConfig.burst_size = 4; in MXC_I2S_RevA_TXDMAConfig()
618 advConfig.burst_size = 2; in MXC_I2S_RevA_TXDMAConfig()
624 advConfig.burst_size = 1; in MXC_I2S_RevA_TXDMAConfig()
630 advConfig.burst_size = 1; in MXC_I2S_RevA_TXDMAConfig()
635 advConfig.burst_size = 4; in MXC_I2S_RevA_TXDMAConfig()
641 advConfig.ch = channel; in MXC_I2S_RevA_TXDMAConfig()
642 advConfig.prio = MXC_DMA_PRIO_HIGH; // 0 in MXC_I2S_RevA_TXDMAConfig()
643 advConfig.reqwait_en = 0; in MXC_I2S_RevA_TXDMAConfig()
644 advConfig.tosel = MXC_DMA_TIMEOUT_4_CLK; // 0 in MXC_I2S_RevA_TXDMAConfig()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/DMA/
Ddma_revb.c167 int MXC_DMA_RevB_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_RevB_AdvConfigChannel() argument
169 if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) { in MXC_DMA_RevB_AdvConfigChannel()
170 dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here in MXC_DMA_RevB_AdvConfigChannel()
172 dma_resource[advConfig.ch].regs->ctrl |= in MXC_DMA_RevB_AdvConfigChannel()
173 ((advConfig.reqwait_en ? MXC_F_DMA_CTRL_TO_WAIT : 0) | advConfig.prio | in MXC_DMA_RevB_AdvConfigChannel()
174 advConfig.tosel | advConfig.pssel | in MXC_DMA_RevB_AdvConfigChannel()
175 (((advConfig.burst_size - 1) << MXC_F_DMA_CTRL_BURST_SIZE_POS) & in MXC_DMA_RevB_AdvConfigChannel()
Ddma_reva.c200 int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_RevA_AdvConfigChannel() argument
202 if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) { in MXC_DMA_RevA_AdvConfigChannel()
203 dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here in MXC_DMA_RevA_AdvConfigChannel()
205 dma_resource[advConfig.ch].regs->ctrl |= in MXC_DMA_RevA_AdvConfigChannel()
206 ((advConfig.reqwait_en ? MXC_F_DMA_REVA_CTRL_TO_WAIT : 0) | advConfig.prio | in MXC_DMA_RevA_AdvConfigChannel()
207 advConfig.tosel | advConfig.pssel | in MXC_DMA_RevA_AdvConfigChannel()
208 (((advConfig.burst_size - 1) << MXC_F_DMA_REVA_CTRL_BURST_SIZE_POS) & in MXC_DMA_RevA_AdvConfigChannel()
Ddma_me16.c65 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
67 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_ai87.c69 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
71 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_es17.c65 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
67 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me10.c68 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
70 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me11.c71 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
73 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me12.c69 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
71 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me13.c65 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
67 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me15.c65 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
67 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me17.c69 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
71 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me18.c69 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
71 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me21.c65 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
67 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me55.c65 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
67 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_me14.c98 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) in MXC_DMA_AdvConfigChannel() argument
100 return MXC_DMA_RevA_AdvConfigChannel(advConfig); in MXC_DMA_AdvConfigChannel()
Ddma_revb.h35 int MXC_DMA_RevB_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
Ddma_reva.h38 int MXC_DMA_RevA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/SPI/
Dspi_reva1.c938 mxc_dma_adv_config_t advConfig = { in MXC_SPI_RevA1_MasterTransactionDMA() local
1015 advConfig.ch = states[spi_num].channelTx; in MXC_SPI_RevA1_MasterTransactionDMA()
1016 advConfig.burst_size = 2; in MXC_SPI_RevA1_MasterTransactionDMA()
1044 MXC_DMA_AdvConfigChannel(advConfig); in MXC_SPI_RevA1_MasterTransactionDMA()
1057 advConfig.ch = states[spi_num].channelRx; in MXC_SPI_RevA1_MasterTransactionDMA()
1058 advConfig.burst_size = 1; in MXC_SPI_RevA1_MasterTransactionDMA()
1083 MXC_DMA_AdvConfigChannel(advConfig); in MXC_SPI_RevA1_MasterTransactionDMA()
1146 mxc_dma_adv_config_t advConfig = { in MXC_SPI_RevA1_SlaveTransactionDMA() local
1203 advConfig.ch = states[spi_num].channelTx; in MXC_SPI_RevA1_SlaveTransactionDMA()
1204 advConfig.burst_size = 2; in MXC_SPI_RevA1_SlaveTransactionDMA()
[all …]
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Source/CAN/
Dcan_reva.c924 mxc_dma_adv_config_t advConfig; in MXC_CAN_RevA_MessageReadDMA() local
925 advConfig.ch = ch; in MXC_CAN_RevA_MessageReadDMA()
926 advConfig.prio = MXC_DMA_PRIO_HIGH; in MXC_CAN_RevA_MessageReadDMA()
927 advConfig.reqwait_en = 0; in MXC_CAN_RevA_MessageReadDMA()
928 advConfig.tosel = MXC_DMA_TIMEOUT_4_CLK; // 0 in MXC_CAN_RevA_MessageReadDMA()
929 advConfig.pssel = MXC_DMA_PRESCALE_DISABLE; // 0 in MXC_CAN_RevA_MessageReadDMA()
930 advConfig.burst_size = 4; in MXC_CAN_RevA_MessageReadDMA()
931 MXC_DMA_AdvConfigChannel(advConfig); in MXC_CAN_RevA_MessageReadDMA()
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Include/MAX32520/
Ddma.h223 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Include/MAX32660/
Ddma.h233 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Include/MAX78002/
Ddma.h243 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Include/MAX78000/
Ddma.h245 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);
/hal_adi-latest/MAX/Libraries/PeriphDrivers/Include/MAX32675/
Ddma.h245 int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig);

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