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Searched refs:Control (Results 1 – 25 of 34) sorted by relevance

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/cmsis_6-latest/CMSIS/Documentation/Doxygen/Driver/src/
DDriver_MCI.c725 MCIdrv->Control(ARM_MCI_DATA_TIMEOUT, 12500000);
729 MCIdrv->Control(ARM_MCI_CSS_TIMEOUT, 1000000);
733 MCIdrv->Control(ARM_MCI_MONITOR_SDIO_INTERRUPT, 1);
735 MCIdrv->Control(ARM_MCI_MONITOR_SDIO_INTERRUPT, 0);
739 MCIdrv->Control(ARM_MCI_CONTROL_READ_WAIT, 1);
741 MCIdrv->Control(ARM_MCI_CONTROL_READ_WAIT, 0);
744 MCIdrv->Control(ARM_MCI_SUSPEND_TRANSFER, 0/*argument not used*/);
747 MCIdrv->Control(ARM_MCI_RESUME_TRANSFER, 0/*argument not used*/);
DSPI_Demo.c67 …SPIdrv->Control(ARM_SPI_MODE_MASTER | ARM_SPI_CPOL1_CPHA1 | ARM_SPI_MSB_LSB | ARM_SPI_SS_MASTER_SW… in mySPI_Thread()
70 SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE); in mySPI_Thread()
76 SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE); in mySPI_Thread()
85 SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE); in mySPI_Thread()
88 SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_ACTIVE); in mySPI_Thread()
96 SPIdrv->Control(ARM_SPI_CONTROL_SS, ARM_SPI_SS_INACTIVE); in mySPI_Thread()
DUSART_Demo.c63 USARTdrv->Control(ARM_USART_MODE_ASYNCHRONOUS | in myUART_Thread()
70 USARTdrv->Control (ARM_USART_CONTROL_TX, 1); in myUART_Thread()
71 USARTdrv->Control (ARM_USART_CONTROL_RX, 1); in myUART_Thread()
DI2C_Demo.c121 I2Cdrv->Control (ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST); in EEPROM_Initialize()
122 I2Cdrv->Control (ARM_I2C_BUS_CLEAR, 0); in EEPROM_Initialize()
DNAND_Demo.c47 drv->Control (0U, ARM_NAND_BUS_MODE, ARM_NAND_BUS_SDR); in PowerOn()
50 drv->Control (0U, ARM_NAND_BUS_DATA_WIDTH, ARM_NAND_BUS_DATA_WIDTH_8); in PowerOn()
DI2C_SlaveDemo.c24 I2Cdrv->Control(ARM_I2C_OWN_ADDRESS, 0x78); in main()
/cmsis_6-latest/CMSIS/Documentation/Doxygen/Core/src/
Dref_data_structs.txt71 \brief Union type to access the Control Registers (CONTROL).
110 \brief Structure type to access the System Control Block (SCB).
115 …__IOM uint32_t ICSR; ///< Offset: 0x004 (R/W) Interrupt Control and State Regis…
117 … AIRCR; ///< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
118 __IOM uint32_t SCR; ///< Offset: 0x010 (R/W) System Control Register
119 __IOM uint32_t CCR; ///< Offset: 0x014 (R/W) Configuration Control Register
121 …__IOM uint32_t SHCSR; ///< Offset: 0x024 (R/W) System Handler Control and State …
134 …__IOM uint32_t CPACR; ///< Offset: 0x088 (R/W) Coprocessor Access Control Regist…
142 \brief Structure type to access the System Control and ID Register not in the SCB.
149 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register
[all …]
Dregister_mapping.md59 <th colspan="4">System Control Block (SCB) Register Access</th>
71 <td>Interrupt Control and State Register</td>
83 <td>Application Interrupt and Reset Control Register</td>
89 <td>System Control Register</td>
95 <td>Configuration and Control Register</td>
107 <td>System Handler Control and State Register</td>
179 <td>Coprocessor Access Control Register</td>
182 <th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access</th>
194 <td>Auxiliary Control Register</td>
197 <th colspan="4">System Timer (SysTick) Control and Status Register Access</th>
[all …]
Dref_deprecated.txt22 …__IOM uint32_t DHCSR; ///< Offset: 0x000 (R/W) Debug Halting Control and Status …
25 …32_t DEMCR; ///< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
26 … ///< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register (Armv8.1…
27 …__IOM uint32_t DAUTHCTRL; ///< Offset: 0x014 (R/W) Debug Authentication Control Regi…
28 …__IOM uint32_t DSCSR; ///< Offset: 0x018 (R/W) Debug Security Control and Status…
Dref_peripheral.txt57 __OM uint8_t FCR; /* Offset: 0x008 ( /W) FIFO Control Register */
59 __IOM uint8_t LCR; /* Offset: 0x00C (R/W) Line Control Register */
65 __IOM uint32_t ACR; /* Offset: 0x020 (R/W) Autobaud Control Register */
66 __IOM uint8_t ICR; /* Offset: 0x024 (R/W) IrDA Control Register */
109 __IOM uint32_t CTRL; /* Offset: 0x000 (R/W) SysTick Control and Status Register */
169 Bit field definitions for register CPUID in SCB (System Control Block).
Dref_trustzone.txt27 \brief Get Control register (non-secure)
28 \details Returns the content of the non-secure Control register when in secure mode.
29 \return non-secure Control register value
36 \brief Set Control register (non-secure)
37 \details Writes the given value to the non-secure Control register when in secure state.
38 \param [in] control Control register value to set
Dref_version_ctrl.txt3 \defgroup version_control_gr Version Control
Dref_cm7_cache.txt12 System Control Space (SCS) region of the internal PPB memory space.
/cmsis_6-latest/CMSIS/Documentation/Doxygen/Core_A/src/
Dref_timer.txt10 /** \brief Physical Timer Control register */
100 …gister decrements if the timer is enabled using the timer enable bit in the Timer Control Register.
109 generation is enabled in the Timer Control Register.
115 \details Private Timer Control Register
154 \details Watchdog Control Register
187 Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.
Dref_core_reg.txt12 \defgroup CMSIS_ACTLR Auxiliary Control Register (ACTLR)
205 \defgroup CMSIS_CPACR Coprocessor Access Control Register (CPACR)
481 \defgroup CMSIS_DACR Domain Access Control Register (DACR)
560 \defgroup CMSIS_FPEXC Floating-Point Exception Control register (FPEXC)
590 \defgroup CMSIS_FPSCR Floating-point Status and Control Register (FPSCR)
811 \defgroup CMSIS_CNTP_CTL PL1 Physical Timer Control register (CNTP_CTL)
831 This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
835 This function returns the value of the PL1 Physical Timer Control Register. (CNTP_CTL).
951 \defgroup CMSIS_SCTLR System Control Register (SCTLR)
Dref_core_ca.txt37 __O uint32_t UART_CR; // Offset: 0x0000 ( /W) Control Register
86 __IOM uint32_t C_CTLR; // Offset: 0x0000 (R/W) CPU Interface Control Register
233 \defgroup version_control_gr Version Control
/cmsis_6-latest/CMSIS/Driver/Include/
DDriver_I2C.h215 …int32_t (*Control) (uint32_t control, uint32_t arg); … member
DDriver_SPI.h245 …int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref A… member
DDriver_ETH_MAC.h300 …int32_t (*Control) (uint32_t control, uint32_t arg); … member
DDriver_MCI.h357 …int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_… member
DDriver_SAI.h306 …int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Po… member
DDriver_USART.h336 …int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \re… member
DDriver_CAN.h377 int32_t (*Control) (uint32_t control, member
DDriver_NAND.h416 …int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); … member
/cmsis_6-latest/CMSIS/Documentation/Doxygen/RTOS2/src/
Dref_cmsis_os2_kernel.txt2 // ==== Kernel Control ====
4 \addtogroup CMSIS_RTOS_KernelCtrl Kernel Information and Control
8 The kernel Information and Control function group allows to:
531 status = osKernelProtect(4U); // Enable Kernel Control for threads with safety class 4 or higher

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