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Searched refs:CPDLPSTATE (Results 1 – 9 of 9) sorted by relevance

/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM55NS/RTE/Device/ARMCM55/
Dsystem_ARMCM55.c86 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); in SystemInit()
90 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; in SystemInit()
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM55/RTE/Device/ARMCM55/
Dsystem_ARMCM55.c86 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); in SystemInit()
90 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; in SystemInit()
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM55S/RTE/Device/ARMCM55/
Dsystem_ARMCM55.c86 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); in SystemInit()
90 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; in SystemInit()
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM85NS/RTE/Device/ARMCM85/
Dsystem_ARMCM85.c74 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | in SystemInit()
85 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; in SystemInit()
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM85S/RTE/Device/ARMCM85/
Dsystem_ARMCM85.c74 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | in SystemInit()
85 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; in SystemInit()
/cmsis_6-latest/CMSIS/CoreValidation/Layer/Target/CM85/RTE/Device/ARMCM85/
Dsystem_ARMCM85.c74 PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | in SystemInit()
85 PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; in SystemInit()
/cmsis_6-latest/CMSIS/Core/Include/
Dcore_cm52.h1579 …__IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State… member
Dcore_cm55.h1532 …__IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State… member
Dcore_cm85.h1526 …__IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State… member