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Searched refs:__RAM_BASE (Results 1 – 24 of 24) sorted by relevance

/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA5/
DARMCA5.sct24 RW_DATA __RAM_BASE __RW_DATA_SIZE
27 ZI_DATA (__RAM_BASE+
31 ARM_LIB_HEAP (__RAM_BASE
36 ARM_LIB_STACK (__RAM_BASE
45 UND_STACK (__RAM_BASE
53 ABT_STACK (__RAM_BASE
60 SVC_STACK (__RAM_BASE
66 IRQ_STACK (__RAM_BASE
71 FIQ_STACK (__RAM_BASE
Dmem_ARMCA5.h71 #define __RAM_BASE 0x80200000 macro
Dmmu_ARMCA5.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA7/
DARMCA7.sct24 RW_DATA __RAM_BASE __RW_DATA_SIZE
27 ZI_DATA (__RAM_BASE+
31 ARM_LIB_HEAP (__RAM_BASE
36 ARM_LIB_STACK (__RAM_BASE
45 UND_STACK (__RAM_BASE
53 ABT_STACK (__RAM_BASE
60 SVC_STACK (__RAM_BASE
66 IRQ_STACK (__RAM_BASE
71 FIQ_STACK (__RAM_BASE
Dmem_ARMCA7.h71 #define __RAM_BASE 0x80200000 macro
Dmmu_ARMCA7.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCA9/
DARMCA9.sct24 RW_DATA __RAM_BASE __RW_DATA_SIZE
27 ZI_DATA (__RAM_BASE+
31 ARM_LIB_HEAP (__RAM_BASE
36 ARM_LIB_STACK (__RAM_BASE
45 UND_STACK (__RAM_BASE
53 ABT_STACK (__RAM_BASE
60 SVC_STACK (__RAM_BASE
66 IRQ_STACK (__RAM_BASE
71 FIQ_STACK (__RAM_BASE
Dmem_ARMCA9.h71 #define __RAM_BASE 0x80200000 macro
Dmmu_ARMCA9.c172 …MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sec… in MMU_CreateTranslationTable()
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM0P/
DARMCM0plus_gcc.ld20 __RAM_BASE = 0x20000000; symbol
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM4/
DARMCM4_gcc.ld20 __RAM_BASE = 0x20000000; symbol
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM0P/
DARMCM0plus_gcc.ld20 __RAM_BASE = 0x20000000; symbol
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCM0plus_gcc.ld.base@2.2.020 __RAM_BASE = 0x20000000;
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/dsppp/RTE/Device/ARMCM4/
DARMCM4_gcc.ld20 __RAM_BASE = 0x20000000; symbol
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
DARMCM4_gcc.ld.base@2.2.020 __RAM_BASE = 0x20000000;
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM7/
DARMCM7_gcc.ld20 __RAM_BASE = 0x20000000; symbol
39 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM33/
DARMCM33_gcc.ld20 __RAM_BASE = 0x20000000; symbol
45 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM3/
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM4_FP/
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM7_DP/
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
63 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM23/
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
69 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM33_DSP_FP/
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
69 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE
/cmsis-dsp-latest/Testing/cmsis_build/RTE/Device/ARMCM55/
Dgcc_arm.ld44 __RAM_BASE = 0x20000000; symbol
69 RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE