Home
last modified time | relevance | path

Searched refs:DDR4_BLK5_BASE_S (Results 1 – 4 of 4) sorted by relevance

/cmsis-dsp-3.7.0-3.6.0/Testing/cmsis_build/RTE/Device/SSE-300-MPS3/
Dplatform_base_address.h183 #define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ macro
251 #define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
252 #define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
253 #define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
/cmsis-dsp-3.7.0-3.6.0/Testing/cmsis_build/RTE/Device/SSE-310-MPS3/
Dplatform_base_address.h179 #define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ macro
247 #define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
248 #define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
249 #define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
/cmsis-dsp-3.7.0-3.6.0/Examples/cmsis_build/RTE/Device/SSE-300-MPS3/
Dplatform_base_address.h193 #define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ macro
261 #define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
262 #define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
263 #define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
/cmsis-dsp-3.7.0-3.6.0/Examples/cmsis_build/RTE/Device/SSE-310-MPS3/
Dplatform_base_address.h179 #define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ macro
247 #define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
248 #define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
249 #define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)