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Searched refs:__ASM (Results 1 – 13 of 13) sorted by relevance

/cmsis-3.5.0/CMSIS/Core/Include/
Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
228 #define __NOP() __ASM volatile ("nop")
234 #define __WFI() __ASM volatile ("wfi":::"memory")
242 #define __WFE() __ASM volatile ("wfe":::"memory")
249 #define __SEV() __ASM volatile ("sev")
260 __ASM volatile ("isb 0xF":::"memory"); in __ISB()
271 __ASM volatile ("dsb 0xF":::"memory"); in __DSB()
282 __ASM volatile ("dmb 0xF":::"memory"); in __DMB()
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Dcmsis_armclang_ltm.h33 #ifndef __ASM
34 #define __ASM __asm macro
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
276 #define __BKPT(value) __ASM volatile ("bkpt "#value)
423 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
438 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRBT()
453 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRHT()
468 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRT()
481 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
493 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
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Dcmsis_armclang.h33 #ifndef __ASM
34 #define __ASM __asm macro
110 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
278 #define __BKPT(value) __ASM volatile ("bkpt "#value)
429 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
444 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRBT()
459 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRHT()
474 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); in __LDRT()
487 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
499 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
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Dcmsis_armcc.h57 #ifndef __ASM
58 #define __ASM __asm macro
208 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16()
223 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) in __REVSH()
410 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) in __RRX()
557 register uint32_t __regControl __ASM("control"); in __get_CONTROL()
569 register uint32_t __regControl __ASM("control"); in __set_CONTROL()
582 register uint32_t __regIPSR __ASM("ipsr"); in __get_IPSR()
594 register uint32_t __regAPSR __ASM("apsr"); in __get_APSR()
606 register uint32_t __regXPSR __ASM("xpsr"); in __get_xPSR()
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Dcmsis_iccarm.h112 #ifndef __ASM
113 #define __ASM __asm macro
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
632 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); in __RRX()
872 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRBT()
879 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRHT()
886 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); in __LDRT()
892 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); in __STRBT()
897 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); in __STRHT()
902 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); in __STRT()
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Dcmsis_compiler.h70 #ifndef __ASM
71 #define __ASM __asm macro
142 #ifndef __ASM
143 #define __ASM __asm macro
211 #ifndef __ASM
212 #define __ASM _asm macro
/cmsis-3.5.0/CMSIS/Core_A/Include/
Dcmsis_gcc.h40 #ifndef __ASM
41 #define __ASM __asm macro
108 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
116 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB16()
125 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB8()
134 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD16()
142 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
150 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD()
158 __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSAX()
166 __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSAX()
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Dcmsis_armclang.h31 #ifndef __ASM
32 #define __ASM __asm macro
102 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
190 #define __BKPT(value) __ASM volatile ("bkpt "#value)
341 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD()
349 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB()
363 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
378 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
388 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
398 __ASM volatile ("cpsie f" : : : "memory"); in __enable_fault_irq()
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Dcmsis_armcc.h38 #ifndef __ASM
39 #define __ASM __asm macro
144 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) in __REV16()
158 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) in __REVSH()
335 register uint32_t __regfpscr __ASM("fpscr"); in __get_FPSCR()
350 register uint32_t __regfpscr __ASM("fpscr"); in __set_FPSCR()
362 register uint32_t __regCPSR __ASM("cpsr"); in __get_CPSR()
372 register uint32_t __regCPSR __ASM("cpsr"); in __set_CPSR()
387 __STATIC_INLINE __ASM void __set_mode(uint32_t mode) in __set_mode()
397 __STATIC_INLINE __ASM uint32_t __get_SP(void) in __get_SP()
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Dcmsis_iccarm.h71 #ifndef __ASM
72 #define __ASM __asm macro
76 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
271 __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
274 __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
408 __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); in __set_mode()
425 __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); in __RRX()
439 __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); in __get_FPEXC()
449 __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); in __set_FPEXC()
455__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "mem…
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Dcmsis_compiler.h64 #ifndef __ASM
65 #define __ASM __asm macro
117 #ifndef __ASM
118 #define __ASM __asm macro
163 #ifndef __ASM
164 #define __ASM _asm macro
/cmsis-3.5.0/CMSIS/Core_R/Include/
Dcmsis_gcc.h41 #ifndef __ASM
42 #define __ASM __asm macro
109 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
117 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB16()
125 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB8()
133 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD16()
141 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
149 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD()
157 __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSAX()
165 __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSAX()
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Dcmsis_compiler.h64 #ifndef __ASM
65 #define __ASM __asm macro
117 #ifndef __ASM
118 #define __ASM __asm macro
163 #ifndef __ASM
164 #define __ASM _asm macro