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Searched refs:wdt_it8xxx2_regs (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/drivers/watchdog/
Dwdt_ite_it8xxx2.c26 struct wdt_it8xxx2_regs *base;
44 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_install_timeout()
76 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_setup()
146 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_feed()
181 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_disable()
204 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_isr()
249 struct wdt_it8xxx2_regs *const inst = wdt_config->base; in wdt_it8xxx2_init()
277 .base = (struct wdt_it8xxx2_regs *)DT_INST_REG_ADDR(0),
/Zephyr-latest/soc/ite/ec/common/
Dcheck_regs.c213 IT8XXX2_REG_SIZE_CHECK(wdt_it8xxx2_regs, 0x0f);
214 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ETWCFG, 0x01);
215 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1PSR, 0x02);
216 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1CNTLHR, 0x03);
217 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET1CNTLLR, 0x04);
218 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ETWCTRL, 0x05);
219 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDCNTLR, 0x06);
220 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDKEYR, 0x07);
221 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, EWDCNTHR, 0x09);
222 IT8XXX2_REG_OFFSET_CHECK(wdt_it8xxx2_regs, ET2PSR, 0x0a);
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Dchip_chipregs.h351 ((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
354 struct wdt_it8xxx2_regs { struct
/Zephyr-latest/drivers/timer/
Dite_it8xxx2_timer.c56 #define WDT_REG (struct wdt_it8xxx2_regs *)(WDT_BASE)
121 struct wdt_it8xxx2_regs *const timer2_reg = WDT_REG; in timer_5ms_one_shot()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_ite_it8xxx2.c253 struct wdt_it8xxx2_regs *const wdt_regs = WDT_IT8XXX2_REGS_BASE; in soc_interrupt_init()