Searched refs:vco_input_range (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_h5.c | 384 static uint32_t get_vco_output_range(uint32_t vco_input_range) in get_vco_output_range() argument 386 if (vco_input_range == LL_RCC_PLLINPUTRANGE_1_2) { in get_vco_output_range() 434 uint32_t vco_input_range; in set_up_plls() local 465 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls() 470 vco_output_range = get_vco_output_range(vco_input_range); in set_up_plls() 475 LL_RCC_PLL1_SetVCOInputRange(vco_input_range); in set_up_plls() 522 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls() 527 vco_output_range = get_vco_output_range(vco_input_range); in set_up_plls() 532 LL_RCC_PLL2_SetVCOInputRange(vco_input_range); in set_up_plls() 576 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls() [all …]
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| D | clock_stm32_ll_h7.c | 347 static uint32_t get_vco_output_range(uint32_t vco_input_range) argument 349 if (vco_input_range == LL_RCC_PLLINPUTRANGE_1_2) { 771 uint32_t vco_input_range; local 834 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); 839 vco_output_range = get_vco_output_range(vco_input_range); 843 LL_RCC_PLL1_SetVCOInputRange(vco_input_range); 882 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range); 887 vco_output_range = get_vco_output_range(vco_input_range); 891 LL_RCC_PLL2_SetVCOInputRange(vco_input_range); 936 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range); [all …]
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| D | clock_stm32_ll_u5.c | 517 uint32_t vco_input_range; in set_up_plls() local 554 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls() 562 LL_RCC_PLL1_SetVCOInputRange(vco_input_range); in set_up_plls() 609 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls() 616 LL_RCC_PLL2_SetVCOInputRange(vco_input_range); in set_up_plls() 661 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls() 668 LL_RCC_PLL3_SetVCOInputRange(vco_input_range); in set_up_plls()
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| D | clock_stm32_ll_wba.c | 387 uint32_t vco_input_range; in set_up_plls() local 403 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range); in set_up_plls() 410 LL_RCC_PLL1_SetVCOInputRange(vco_input_range); in set_up_plls()
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