Searched refs:uncached (Results 1 – 15 of 15) sorted by relevance
| /Zephyr-latest/tests/boards/intel_adsp/cache/src/ |
| D | main.c | 13 uint32_t *cached, *uncached; in ZTEST() local
16 uncached = sys_cache_uncached_ptr_get(cached); in ZTEST()
19 *uncached = 40; in ZTEST()
23 zassert_equal(*uncached, 40, NULL); in ZTEST()
29 zassert_equal(*uncached, 42, NULL); in ZTEST()
33 *uncached = 80; in ZTEST()
37 zassert_equal(*uncached, 80, NULL); in ZTEST()
43 zassert_equal(*uncached, 80, NULL); in ZTEST()
49 zassert_equal(*uncached, 82, NULL); in ZTEST()
51 *uncached = 100; in ZTEST()
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| /Zephyr-latest/doc/hardware/cache/ |
| D | guide.rst | 62 compromise if performance on the uncached memory is not critical to the
77 using a dedicated uncached region of memory, the linker needs to be instructed
83 /* SRAM4 marked as uncached in device tree */
97 Zephyr has the ability to automatically define an uncached region in memory and
100 region will be configured as uncached by the MPU driver during initialization.
101 This is a simpler option than explicitly declaring a region of memory uncached
110 linker region and configure it as uncached.
112 * Add the ``__nocache`` attribute at the end of any uncached buffer definition:
135 more efficient to place them in an uncached region, as unrelated data packed
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| D | index.rst | 49 specify individual global variables as uncached using ``__nocache``. This will
51 region in memory and the MPU driver will configure that region as uncached.
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| /Zephyr-latest/arch/xtensa/ |
| D | Kconfig | 58 bool "Cached/uncached RPO mapping"
60 Support Cached/uncached RPO mapping.
79 region (0-7) contains the "uncached" mapping.
221 bool "Map memory in cached and uncached region"
224 distinct region, cached and uncached.
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| /Zephyr-latest/doc/develop/sca/ |
| D | sparse.rst | 15 Xtensa architecture. This helps identify cases where cached and uncached
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| /Zephyr-latest/samples/boards/intel/adsp/code_relocation/ |
| D | linker_xtensa_intel_adsp_cavs.ld | 30 * One final detail: SRAM4 actually lives in the "uncached" memory,
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| /Zephyr-latest/kernel/ |
| D | Kconfig.smp | 106 (generally "uncached") memory. Thread stacks will remain
112 Code that creates kernel data structures in uncached regions
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| /Zephyr-latest/drivers/serial/ |
| D | uart_hostlink.c | 150 #define __uncached __attribute__((uncached))
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/ |
| D | Kconfig | 85 uncached memory. Add possibility to place the RX and TX buffers in the
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| /Zephyr-latest/soc/intel/intel_adsp/common/ |
| D | CMakeLists.txt | 72 # Remap uncached section addresses so they appear contiguous
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| /Zephyr-latest/arch/xtensa/core/ |
| D | README_MMU.txt | 153 uncached. So at boot the CPU relies on these TLB entries to provide a
267 page table mappings in the system are set uncached. The OS makes no
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| /Zephyr-latest/soc/intel/intel_adsp/cavs/include/ |
| D | xtensa-cavs-linker.ld | 374 * sections need to be linked in safe/uncached memory but common-rom
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| /Zephyr-latest/soc/intel/intel_adsp/ace/ |
| D | ace-link.ld | 442 * sections need to be linked in safe/uncached memory but common-rom
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| /Zephyr-latest/arch/ |
| D | Kconfig | 409 bool "Support for uncached memory"
1035 point to the same cached/uncached memory at different locations.
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-3.7.rst | 1184 on STM32 F7 & H7 SoC series, as long as DMA buffers are placed in an uncached memory section.
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