Searched refs:tmpreg (Results 1 – 3 of 3) sorted by relevance
98 uint16_t tmpreg = 0; in alt_eth_phy_write_register() local109 tmpreg = 0; in alt_eth_phy_write_register()111 tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); in alt_eth_phy_write_register()113 tmpreg |= EMAC_GMAC_GMII_ADDR_GR_SET(phy_reg); in alt_eth_phy_write_register()115 tmpreg |= EMAC_GMAC_GMII_ADDR_GW_SET_MSK; in alt_eth_phy_write_register()117 tmpreg |= EMAC_GMAC_GMII_ADDR_CR_SET(EMAC_GMAC_GMII_ADDR_CR_E_DIV102); in alt_eth_phy_write_register()119 tmpreg |= EMAC_GMAC_GMII_ADDR_GB_SET(EMAC_GMAC_GMII_ADDR_GB_SET_MSK); in alt_eth_phy_write_register()124 sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()130 tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr)); in alt_eth_phy_write_register()131 } while ((tmpreg & EMAC_GMAC_GMII_ADDR_GB_SET_MSK) && (timeout < PHY_WRITE_TO)); in alt_eth_phy_write_register()[all …]
121 uint32_t tmpreg; in eth_cyclonev_set_mac_addr() local132 tmpreg = ((uint32_t)address[5] << 8) | (uint32_t)address[4]; in eth_cyclonev_set_mac_addr()135 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_HIGH_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()138 tmpreg = ((uint32_t)address[3] << 24) | ((uint32_t)address[2] << 16) | in eth_cyclonev_set_mac_addr()142 sys_write32(tmpreg, EMAC_GMAC_MAC_ADDR_LOW_ADDR(p->base_addr, n)); in eth_cyclonev_set_mac_addr()855 uint32_t tmpreg = 0, interrupt_mask; in eth_cyclonev_probe() local905 sys_write32((tmpreg | EMAC_DMA_MODE_FB_SET_MSK /* Fixed Burst */ in eth_cyclonev_probe()914 tmpreg = sys_read32(EMAC_DMAGRP_AXI_BUS_MODE_ADDR(p->base_addr)); in eth_cyclonev_probe()917 tmpreg | EMAC_DMAGRP_AXI_BUS_MODE_BLEN16_SET_MSK, in eth_cyclonev_probe()
159 uint64_t tmpreg; in arch_user_mode_enter() local190 : [tmp] "=&r" (tmpreg) in arch_user_mode_enter()
