98 	uint16_t tmpreg = 0;  in alt_eth_phy_write_register()  local
109 	tmpreg = 0;  in alt_eth_phy_write_register()
111 	tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr);  in alt_eth_phy_write_register()
113 	tmpreg |= EMAC_GMAC_GMII_ADDR_GR_SET(phy_reg);  in alt_eth_phy_write_register()
115 	tmpreg |= EMAC_GMAC_GMII_ADDR_GW_SET_MSK;  in alt_eth_phy_write_register()
117 	tmpreg |= EMAC_GMAC_GMII_ADDR_CR_SET(EMAC_GMAC_GMII_ADDR_CR_E_DIV102);  in alt_eth_phy_write_register()
119 	tmpreg |= EMAC_GMAC_GMII_ADDR_GB_SET(EMAC_GMAC_GMII_ADDR_GB_SET_MSK);  in alt_eth_phy_write_register()
124 	sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr));  in alt_eth_phy_write_register()
130 		tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr));  in alt_eth_phy_write_register()
131 	} while ((tmpreg & EMAC_GMAC_GMII_ADDR_GB_SET_MSK) && (timeout < PHY_WRITE_TO));  in alt_eth_phy_write_register()
145 	uint16_t tmpreg = 0;  in alt_eth_phy_read_register()  local
156 	tmpreg = 0;  in alt_eth_phy_read_register()
158 	tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr);  in alt_eth_phy_read_register()
160 	tmpreg |= EMAC_GMAC_GMII_ADDR_GR_SET(phy_reg);  in alt_eth_phy_read_register()
162 	tmpreg &= EMAC_GMAC_GMII_ADDR_GW_CLR_MSK;  in alt_eth_phy_read_register()
164 	tmpreg |= EMAC_GMAC_GMII_ADDR_CR_SET(EMAC_GMAC_GMII_ADDR_CR_E_DIV102);  in alt_eth_phy_read_register()
166 	tmpreg |= EMAC_GMAC_GMII_ADDR_GB_SET(EMAC_GMAC_GMII_ADDR_GB_SET_MSK);  in alt_eth_phy_read_register()
169 	sys_write32(tmpreg & 0xffff, EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr));  in alt_eth_phy_read_register()
174 		tmpreg = sys_read32(EMAC_GMAC_GMII_ADDR_ADDR(p->base_addr));  in alt_eth_phy_read_register()
175 	} while ((tmpreg & EMAC_GMAC_GMII_ADDR_GB_SET_MSK) && (timeout < PHY_READ_TO));  in alt_eth_phy_read_register()