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Searched refs:sys_set_bit (Results 1 – 25 of 33) sorted by relevance

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/Zephyr-latest/include/zephyr/arch/common/
Dsys_bitops.h24 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() function
65 sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_set_bit()
86 sys_set_bit(addr, bit); in sys_test_and_set_bit()
/Zephyr-latest/drivers/counter/
Dcounter_dw_timer.c103 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_irq_handler()
124 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_start()
128 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_start()
191 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_set_top_value()
204 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT); in counter_dw_timer_set_top_value()
208 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_set_top_value()
257 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT); in counter_dw_timer_set_alarm()
261 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_set_alarm()
/Zephyr-latest/drivers/gpio/
Dgpio_stellaris.c95 sys_set_bit(GPIO_REG_ADDR(base, GPIO_DIR_OFFSET), pin); in gpio_stellaris_configure()
97 sys_set_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin); in gpio_stellaris_configure()
101 sys_set_bit(GPIO_REG_ADDR(base, GPIO_DEN_OFFSET), pin); in gpio_stellaris_configure()
208 sys_set_bit(GPIO_REG_ADDR(base, GPIO_IM_OFFSET), pin); in gpio_stellaris_pin_interrupt_configure()
213 sys_set_bit(GPIO_REG_ADDR(base, GPIO_IS_OFFSET), pin); in gpio_stellaris_pin_interrupt_configure()
217 sys_set_bit(GPIO_REG_ADDR(base, GPIO_IBE_OFFSET), pin); in gpio_stellaris_pin_interrupt_configure()
219 sys_set_bit(GPIO_REG_ADDR(base, GPIO_IEV_OFFSET), pin); in gpio_stellaris_pin_interrupt_configure()
Dgpio_iproc.c54 sys_set_bit(base + IPROC_GPIO_OUT_EN_OFFSET, pin); in gpio_iproc_configure()
134 sys_set_bit(base + IPROC_GPIO_INT_TYPE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
139 sys_set_bit(base + IPROC_GPIO_INT_DE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
143 sys_set_bit(base + IPROC_GPIO_INT_EDGE_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
153 sys_set_bit(base + IPROC_GPIO_INT_MSK_OFFSET, pin); in gpio_iproc_pin_interrupt_configure()
Dgpio_rp1.c94 sys_set_bit(RIO_OE_SET(data->rio_base), pin); in gpio_rp1_pin_configure()
99 sys_set_bit(RIO_OUT_SET(data->rio_base), pin); in gpio_rp1_pin_configure()
102 sys_set_bit(RIO_OUT_CLR(data->rio_base), pin); in gpio_rp1_pin_configure()
106 sys_set_bit(RIO_OE_CLR(data->rio_base), pin); in gpio_rp1_pin_configure()
Dgpio_brcmstb.c44 sys_set_bit(data->base + GIO_IODIR, pin); in gpio_brcmstb_pin_configure()
49 sys_set_bit(data->base + GIO_DATA, pin); in gpio_brcmstb_pin_configure()
/Zephyr-latest/drivers/input/
Dinput_tsc_keys.c98 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_START_Pos); in stm32_tsc_start()
122 sys_set_bit((mem_addr_t)&config->tsc->ICR, TSC_ICR_MCEIC_Pos); in stm32_tsc_handle_incoming_data()
130 sys_set_bit((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC_Pos); in stm32_tsc_handle_incoming_data()
218 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSPSC_Pos); in stm32_tsc_init()
223 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SYNCPOL_Pos); in stm32_tsc_init()
228 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_AM_Pos); in stm32_tsc_init()
233 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_IODEF_Pos); in stm32_tsc_init()
238 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSE_Pos); in stm32_tsc_init()
277 sys_set_bit((mem_addr_t)&config->tsc->IOGCSR, group->group - 1); in stm32_tsc_init()
288 sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_TSCE_Pos); in stm32_tsc_init()
/Zephyr-latest/drivers/reset/
Dreset_stm32.c37 sys_set_bit(config->base + STM32_RESET_SET_OFFSET(id), in reset_stm32_line_assert()
48 sys_set_bit(config->base + STM32_RESET_CLR_OFFSET(id), in reset_stm32_line_deassert()
Dreset_gd32.c38 sys_set_bit(config->base + GD32_RESET_ID_OFFSET(id), in reset_gd32_line_assert()
Dreset_numaker.c44 sys_set_bit(config->base + NUMAKER_RESET_IP_OFFSET(id), NUMAKER_RESET_IP_BIT(id)); in reset_numaker_line_assert()
Dreset_intel_socfpga.c53 sys_set_bit(base_address + offset, regbit); in reset_intel_soc_update()
/Zephyr-latest/drivers/ipm/
Dipm_xlnx_ipi.c110 sys_set_bit(config->host_ipi_reg + IPI_ISR, remote_ipi_ch_bit); in xlnx_mailbox_rx_isr()
137 sys_set_bit(config->host_ipi_reg + IPI_TRIG, config->remote_ipi_ch_bit); in xlnx_ipi_send()
172 sys_set_bit(config->host_ipi_reg + IPI_IER, config->remote_ipi_ch_bit); in xlnx_ipi_set_enabled()
174 sys_set_bit(config->host_ipi_reg + IPI_IDR, config->remote_ipi_ch_bit); in xlnx_ipi_set_enabled()
/Zephyr-latest/drivers/spi/
Dspi_sifive.c56 sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_POL); in spi_config()
68 sys_set_bit(SPI_REG(dev, REG_SCKMODE), SF_SCKMODE_PHA); in spi_config()
96 sys_set_bit(SPI_REG(dev, REG_FMT), SF_FMT_ENDIAN); in spi_config()
Dspi_silabs_usart.c151 sys_set_bit(ctrl_reg, _USART_CTRL_CSINV_SHIFT); in spi_config()
165 sys_set_bit(ctrl_reg, _USART_CTRL_MSBF_SHIFT); in spi_config()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_silabs_dbus.c46 sys_set_bit(enable_reg, pins[i].en_bit); in pinctrl_configure_pins()
/Zephyr-latest/drivers/pwm/
Dpwm_sifive.c87 sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMZEROCMP); in pwm_sifive_init()
90 sys_set_bit(PWM_REG(config, REG_PWMCFG), SF_PWMENALWAYS); in pwm_sifive_init()
/Zephyr-latest/include/zephyr/arch/x86/
Darch.h155 static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit) in sys_set_bit() function
208 #define sys_bitfield_set_bit sys_set_bit
/Zephyr-latest/drivers/i2c/
Di2c_dw.h135 #define Z_REG_SET_BIT sys_set_bit
/Zephyr-latest/tests/kernel/common/src/
Dbitfield.c47 sys_set_bit((mem_addr_t)&b1, bit); in ZTEST()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c343 sys_set_bit(rdist + GICR_PWRR, GICR_PWRR_RDAG); in gicv3_rdist_enable()
502 sys_set_bit(GICD_CTLR, GICD_CTRL_NS); in gicv3_dist_init()
559 sys_set_bit(GICD_CTLR, GICD_CTLR_ENABLE_G1S); in gicv3_dist_init()
/Zephyr-latest/drivers/clock_control/
Dclock_control_gd32.c76 sys_set_bit(config->base + GD32_CLOCK_ID_OFFSET(id), in clock_control_gd32_on()
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc_msi.c234 sys_set_bit(PBA_OFFSET(msix_num), PENDING_BIT(msix_num)); in iproc_pcie_generate_msix()
/Zephyr-latest/drivers/dma/
Ddma_silabs_siwx91x.c296 sys_set_bit((mem_addr_t)&cfg->reg->CHNL_SW_REQUEST, channel); in siwx91x_dma_start()
420 sys_set_bit((mem_addr_t)&cfg->reg->CHNL_SW_REQUEST, channel); in siwx91x_dma_isr()
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.c403 sys_set_bit(cdns_params.reg_base + SDHC_CDNS_SRS10, WIDTH_BIT4); in sdhc_cdns_set_ios()
406 sys_set_bit(cdns_params.reg_base + SDHC_CDNS_SRS10, WIDTH_BIT8); in sdhc_cdns_set_ios()
537 sys_set_bit(cdns_params.reg_base + SDHC_CDNS_HRS00, CDNS_HRS00_SWR); in sdhc_cdns_reset()
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.c305 sys_set_bit(CNF_MINICTRL(base_address, DLL_PHY_CTRL), CNF_DLL_PHY_RST_N); in cdns_nand_set_opr_mode()
379 sys_set_bit(CNF_DI(base_address, CONTROL), CNF_DI_PAR_EN); in cdns_nand_init()
385 sys_set_bit(CNF_DI(base_address, CONTROL), CNF_DI_CRC_EN); in cdns_nand_init()
433 sys_set_bit((base_address + INTERRUPT_STATUS_REG), GINTR_ENABLE); in cdns_nand_init()
939 sys_set_bit((base_address + INTR_STATUS), SDMA_TRIGG); in cdns_wait_sdma()

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