Searched refs:sys_clk (Results 1 – 11 of 11) sorted by relevance
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_smartbond.c | 498 int z_smartbond_select_sys_clk(enum smartbond_clock sys_clk) in z_smartbond_select_sys_clk() argument
505 res = smartbond_clock_get_rate(sys_clk, &sys_clock_freq); in z_smartbond_select_sys_clk()
515 if (sys_clk == SMARTBOND_CLK_RC32M) { in z_smartbond_select_sys_clk()
519 } else if (sys_clk == SMARTBOND_CLK_PLL96M) { in z_smartbond_select_sys_clk()
532 } else if (sys_clk == SMARTBOND_CLK_XTAL32M) { in z_smartbond_select_sys_clk()
564 enum smartbond_clock sys_clk; in smartbond_clocks_init() local
582 BUILD_ASSERT(DT_NODE_HAS_STATUS_OKAY(DT_PROP(DT_NODELABEL(sys_clk), clock_src)), in smartbond_clocks_init()
594 clk_id = DT_DEP_ORD(DT_PROP(DT_NODELABEL(sys_clk), clock_src)); in smartbond_clocks_init()
595 sys_clk = smartbond_dt_ord_to_clock(clk_id); in smartbond_clocks_init()
597 (clock_control_subsys_rate_t)smartbond_source_clock(sys_clk)); in smartbond_clocks_init()
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| D | clock_control_renesas_ra_cgc.c | 29 #define sys_clk DT_NODELABEL(cpuclk) macro
31 #define sys_clk DT_NODELABEL(iclk) macro
34 #define SYS_CLOCK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / DT_PROP(sys_clk, div))
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | smartbond_clock_control.h | 43 int z_smartbond_select_sys_clk(enum smartbond_clock sys_clk);
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_b91.c | 31 pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1; in pwm_b91_init()
106 *cycles = sys_clk.pclk * 1000 * 1000 / (reg_pwm_clkdiv + 1); in pwm_b91_get_cycles_per_sec()
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| /Zephyr-latest/samples/drivers/clock_control_xec/src/ |
| D | main.c | 188 struct sys_clk { struct
193 static const struct sys_clk sys_clocks[] = { argument
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| /Zephyr-latest/drivers/i2c/ |
| D | i2c_b91.c | 69 i2c_set_master_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / (4 * i2c_speed))); in i2c_b91_configure()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_b91.c | 303 uint8_t clk_src = b91_config->peripheral_id == PSPI_MODULE ? sys_clk.pclk : sys_clk.hclk; in spi_b91_config()
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| /Zephyr-latest/boards/renesas/da1469x_dk_pro/ |
| D | da1469x_dk_pro.dts | 166 &sys_clk {
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| /Zephyr-latest/drivers/serial/ |
| D | uart_b91.c | 285 uart_b91_cal_div_and_bwpc(cfg->baudrate, sys_clk.pclk * 1000 * 1000, ÷r, &bwpc); in uart_b91_configure()
327 uart_b91_cal_div_and_bwpc(cfg->baud_rate, sys_clk.pclk * 1000 * 1000, ÷r, &bwpc); in uart_b91_driver_init()
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| /Zephyr-latest/boards/renesas/da14695_dk_usb/ |
| D | da14695_dk_usb.dts | 181 &sys_clk {
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| /Zephyr-latest/dts/arm/renesas/smartbond/ |
| D | da1469x.dtsi | 91 sys_clk: sys_clk { label
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