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Searched refs:sys_clear_bits (Results 1 – 21 of 21) sorted by relevance

/Zephyr-latest/drivers/gpio/
Dgpio_rp1.c83 sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OEOVER_MASK); in gpio_rp1_pin_configure()
86 sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_OUTOVER_MASK); in gpio_rp1_pin_configure()
89 sys_clear_bits(GPIO_CTRL(data->gpio_base, pin), GPIO_CTRL_FUNCSEL_MASK); in gpio_rp1_pin_configure()
95 sys_clear_bits(PADS_CTRL(data->pads_base, pin), in gpio_rp1_pin_configure()
112 sys_clear_bits(PADS_CTRL(data->pads_base, pin), in gpio_rp1_pin_configure()
138 sys_clear_bits(RIO_OUT_SET(data->rio_base), mask); in gpio_rp1_port_set_masked_raw()
141 sys_clear_bits(RIO_OUT_CLR(data->rio_base), (value & mask)); in gpio_rp1_port_set_masked_raw()
151 sys_clear_bits(RIO_OUT_CLR(data->rio_base), pins); in gpio_rp1_port_set_bits_raw()
161 sys_clear_bits(RIO_OUT_SET(data->rio_base), pins); in gpio_rp1_port_clear_bits_raw()
176 sys_clear_bits(RIO_OUT_CLR(data->rio_base), val ^ pins); in gpio_rp1_port_toggle_bits()
[all …]
Dgpio_altera_pio.c94 sys_clear_bits(addr, BIT(pin)); in gpio_altera_configure()
182 sys_clear_bits(addr, mask); in gpio_altera_port_clear_bits_raw()
230 sys_clear_bits(addr, BIT(pin)); in gpio_altera_pin_interrupt_configure()
273 sys_clear_bits(addr, port_value); in gpio_altera_irq_handler()
Dgpio_brcmstb.c72 sys_clear_bits(data->base + GIO_DATA, mask); in gpio_brcmstb_port_set_masked_raw()
91 sys_clear_bits(data->base + GIO_DATA, pins); in gpio_brcmstb_port_clear_bits_raw()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_mco.c43 sys_clear_bits( in stm32_mco_init()
54 sys_clear_bits( in stm32_mco_init()
Dclock_agilex_ll.c22 #define mmio_clrbits_32(addr, mask) sys_clear_bits((addr), (mask))
Dclock_stm32_ll_wb0.c245 sys_clear_bits(reg, pclken->enr); in stm32_clock_control_off()
268 sys_clear_bits(reg, STM32_CLOCK_MASK_GET(pclken->enr) << shift); in stm32_clock_control_configure()
Dclock_stm32_ll_wba.c99 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
123 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_common.c288 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
317 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_u5.c187 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
209 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr), in stm32_clock_control_configure()
Dclock_stm32_ll_h7.c425 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
450 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
Dclock_stm32_ll_h5.c181 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, in stm32_clock_control_off()
/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.c66 sys_clear_bits(SPI_TIMIN(cfg->base), TIMIN_SCLK_DIV_MSK); in spi_config()
70 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_SLVMODE_MSK); in spi_config()
73 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_DATA_MERGE_MSK); in spi_config()
77 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_DATA_LEN_MSK); in spi_config()
84 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_CPHA_MSK); in spi_config()
90 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_CPOL_MSK); in spi_config()
97 sys_clear_bits(SPI_TFMAT(cfg->base), TFMAT_LSB_MSK); in spi_config()
101 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_TX_THRES_MSK); in spi_config()
102 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_RX_THRES_MSK); in spi_config()
210 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_disable()
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_cyclonev.c97 sys_clear_bits(SYSMGR_FPGAINTF_INDIV_ADDR, Sysmgr_Fpgaintf_En_3_Emac_Set_Msk[instance]); in eth_cyclonev_reset()
104 sys_clear_bits(RSTMGR_PERMODRST_ADDR, Rstmgr_Permodrst_Emac_Set_Msk[instance]); in eth_cyclonev_reset()
340 sys_clear_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_set_config()
481 sys_clear_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR( in eth_cyclonev_send()
1018 sys_clear_bits(EMAC_GMACGRP_MAC_FRAME_FILTER_ADDR(p->base_addr), in eth_cyclonev_probe()
1106 sys_clear_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_stop()
1112 sys_clear_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_stop()
1116 sys_clear_bits(GMACGRP_MAC_CONFIG_ADDR(p->base_addr), in eth_cyclonev_stop()
1124 sys_clear_bits(EMAC_DMAGRP_OPERATION_MODE_ADDR(p->base_addr), in eth_cyclonev_stop()
/Zephyr-latest/drivers/flash/
Dflash_andes_qspi.c706 sys_clear_bits(QSPI_TFMAT(base), TFMAT_SLVMODE_MSK); in qspi_andes_configure()
709 sys_clear_bits(QSPI_TFMAT(base), TFMAT_DATA_MERGE_MSK); in qspi_andes_configure()
712 sys_clear_bits(QSPI_TFMAT(base), TFMAT_DATA_LEN_MSK); in qspi_andes_configure()
716 sys_clear_bits(QSPI_CTRL(base), CTRL_TX_THRES_MSK); in qspi_andes_configure()
717 sys_clear_bits(QSPI_CTRL(base), CTRL_RX_THRES_MSK); in qspi_andes_configure()
754 sys_clear_bits(QSPI_INTEN(base), IEN_TX_FIFO_MSK); in qspi_andes_irq_handler()
769 sys_clear_bits(QSPI_INTEN(base), IEN_RX_FIFO_MSK); in qspi_andes_irq_handler()
Dflash_cadence_qspi_nor_ll.c37 sys_clear_bits(cad_params->reg_base + CAD_QSPI_CFG, ~CAD_QSPI_CFG_BAUDDIV_MSK); in cad_qspi_set_baudrate_div()
Dflash_cadence_nand_ll.c242 sys_clear_bits(CNF_MINICTRL(base_address, CMN_SETTINGS), in cdns_nand_set_opr_mode()
/Zephyr-latest/include/zephyr/arch/common/
Dsys_bitops.h52 static ALWAYS_INLINE void sys_clear_bits(mem_addr_t addr, unsigned int mask) in sys_clear_bits() function
/Zephyr-latest/drivers/usb/udc/
Dudc_dwc2_vendor_quirks.h78 sys_clear_bits(ggpio_reg, USB_DWC2_GGPIO_STM32_PWRDWN | USB_DWC2_GGPIO_STM32_VBDEN); in stm32f4_fsotg_disable_phy()
286 sys_clear_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); in usbhs_pre_hibernation_exit()
Dudc_dwc2.c327 sys_clear_bits(reg, epmsk); in dwc2_set_epint()
1048 sys_clear_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PWRDNSWTCH); in dwc2_exit_hibernation()
1052 sys_clear_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PWRDNRST_N); in dwc2_exit_hibernation()
1060 sys_clear_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PWRDNCLMP); in dwc2_exit_hibernation()
1075 sys_clear_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PMUINTSEL); in dwc2_exit_hibernation()
1088 sys_clear_bits(gpwrdn_reg, USB_DWC2_GPWRDN_RESTORE); in dwc2_exit_hibernation()
1093 sys_clear_bits(pcgcctl_reg, USB_DWC2_PCGCCTL_RSTPDWNMODULE); in dwc2_exit_hibernation()
1102 sys_clear_bits(gpwrdn_reg, USB_DWC2_GPWRDN_PMUACTV); in dwc2_exit_hibernation()
1741 sys_clear_bits(grstctl_reg, USB_DWC2_GRSTCTL_CSFTRST | USB_DWC2_GRSTCTL_CSFTRSTDONE); in dwc2_core_soft_reset()
2023 sys_clear_bits((mem_addr_t)&base->dctl, USB_DWC2_DCTL_SFTDISCON); in udc_dwc2_enable()
[all …]
/Zephyr-latest/drivers/dai/intel/alh/
Dalh.c101 sys_clear_bits(ADSP_DSPALHO_ADDRESS, DSPALHO_ASO_FLAG | DSPALHO_CSO_FLAG); in alh_release_ownership()
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.c534 sys_clear_bits(cdns_params.reg_base + SDHC_CDNS_SRS11, 0xFFFF); in sdhc_cdns_reset()