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/Zephyr-latest/samples/drivers/adc/adc_sequence/boards/
Dlpcxpresso55s69_cpu0.overlay34 * CH0A (plus side) is routed to P19 pin 4
35 * CH0B (minus side) is routed to P19 pin 2
49 * CH4A is routed to P17 pin 19
62 * CH4B is routed to P18 pin 1
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay21 * CH0A is routed to P19 pin 4
35 * CH4A is routed to P17 pin 19
49 * CH4B is routed to P18 pin 1
Dlpcxpresso55s69_lpc55s69_cpu0_ns.overlay21 * CH0A is routed to P19 pin 4
35 * CH4A is routed to P17 pin 19
49 * CH4B is routed to P18 pin 1
/Zephyr-latest/samples/drivers/adc/adc_dt/boards/
Dlpcxpresso55s69_lpc55s69_cpu0.overlay34 * CH0A (plus side) is routed to P19 pin 4
35 * CH0B (minus side) is routed to P19 pin 2
50 * CH4A is routed to P17 pin 19
64 * CH4B is routed to P18 pin 1
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_qspi_B.overlay7 /* FLEXPWM not routed to LED on this EVK */
/Zephyr-latest/samples/drivers/rtc/boards/
Dqemu_x86_64.overlay8 * The RTC IRQ is not routed to the IOAPIC if the legacy
Dqemu_x86.overlay8 * The RTC IRQ is not routed to the IOAPIC if the legacy
/Zephyr-latest/tests/drivers/rtc/rtc_api/boards/
Dqemu_x86.overlay8 * The RTC IRQ is not routed to the IOAPIC if the legacy
Dqemu_x86_64.overlay8 * The RTC IRQ is not routed to the IOAPIC if the legacy
/Zephyr-latest/boards/shields/v2c_daplink/doc/
Dindex.rst30 routed to USB connector ``J10`` on the :ref:`arty`. For example:
39 CPU will boot from the V2C-DAPLink QSPI NOR flash. The console is routed to USB
/Zephyr-latest/samples/boards/nordic/dynamic_pinctrl/
DREADME.rst18 However, if a certain peripheral is routed to different sets of pins between
42 If you power on the board, the ``uart0`` peripheral is routed to the default
47 routed to the alternative set of pins.
/Zephyr-latest/drivers/ethernet/
DKconfig.sam_gmac36 routed to appropriate queues based on their priority.
39 bool "Force all traffic to be routed through a specific queue"
44 traffic to be routed through a specific hardware queue. With this enabled
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.dw20 that is then routed to the 1st level interrupt controller.
/Zephyr-latest/boards/wiznet/w5500_evb_pico/doc/
Dindex.rst98 The peripherals of the RP2040 SoC can be routed to various pins on the board.
103 Pico. Since GPIO 25 is routed to the on-board LED on, similar to the Raspberry
104 Pi Pico, the blinky example works as intended. The W5500 is routed to the SPI0
105 (P16-P19), with the reset and interrupt signal for the W5500 routed to P20 and
/Zephyr-latest/samples/drivers/clock_control_xec/
DREADME.rst48 XTAL2_32KHZ_IN signal routed to XTAL2 MEC172x pin on Assembly 6915
/Zephyr-latest/boards/weact/blackpill_f401ce/doc/
Dindex.rst92 change for V2.0 specifically where MISO was routed to PB4 for the flash footprint.
93 This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using
/Zephyr-latest/boards/weact/blackpill_f411ce/doc/
Dindex.rst92 change for V2.0 specifically where MISO was routed to PB4 for the flash footprint.
93 This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using
/Zephyr-latest/subsys/net/ip/
Dipv6.c419 int routed; in ipv6_forward_mcast_packet() local
433 routed = net_route_mcast_forward_packet(pkt, hdr); in ipv6_forward_mcast_packet()
435 if (routed < 0) { in ipv6_forward_mcast_packet()
/Zephyr-latest/boards/shields/nrf7002eb/doc/
Dindex.rst49 The nRF7002 EB has a variant which includes the COEX pins. These pins are not be routed to the
/Zephyr-latest/boards/seeed/xiao_rp2040/doc/
Dindex.rst80 The peripherals of the RP2040 SoC can be routed to various pins on the board.
/Zephyr-latest/boards/adafruit/kb2040/doc/
Dindex.rst82 The peripherals of the RP2040 SoC can be routed to various pins on the board.
/Zephyr-latest/boards/adafruit/qt_py_rp2040/doc/
Dindex.rst79 The peripherals of the RP2040 SoC can be routed to various pins on the board.
/Zephyr-latest/boards/raspberrypi/rpi_pico/doc/
Dindex.rst104 The peripherals of the RP2040 SoC can be routed to various pins on the board.
109 RP2040 GPIO lines 23, 24, 25, and 29 are routed to the Infineon module on the W.
110 Since GPIO 25 is routed to the on-board LED on the Pico, but to the Infineon module
/Zephyr-latest/boards/sparkfun/pro_micro_rp2040/doc/
Dindex.rst92 The peripherals of the RP2040 SoC can be routed to various pins on the board.
/Zephyr-latest/boards/shields/x_nucleo_eeprma2/doc/
Dindex.rst12 connector pin assignment. Additionally the pins are routed to dedicated headers

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