1 /*
2  * Copyright (c) 2019 Intel Corporation.
3  * Copyright (c) 2023 Microchip Technology Inc.
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #define DT_DRV_COMPAT microchip_xec_adc
9 
10 #define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
11 #include <zephyr/logging/log.h>
12 LOG_MODULE_REGISTER(adc_mchp_xec);
13 
14 #include <zephyr/drivers/adc.h>
15 #ifdef CONFIG_SOC_SERIES_MEC172X
16 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
17 #endif
18 #include <zephyr/drivers/pinctrl.h>
19 #include <zephyr/pm/device.h>
20 #include <zephyr/pm/policy.h>
21 #include <soc.h>
22 #include <errno.h>
23 #include <zephyr/irq.h>
24 
25 #define ADC_CONTEXT_USES_KERNEL_TIMER
26 #include "adc_context.h"
27 
28 #define XEC_ADC_VREF_ANALOG 3300
29 
30 /* ADC Control Register */
31 #define XEC_ADC_CTRL_SINGLE_DONE_STATUS		BIT(7)
32 #define XEC_ADC_CTRL_REPEAT_DONE_STATUS		BIT(6)
33 #define XER_ADC_CTRL_SOFT_RESET			BIT(4)
34 #define XEC_ADC_CTRL_POWER_SAVER_DIS		BIT(3)
35 #define XEC_ADC_CTRL_START_REPEAT		BIT(2)
36 #define XEC_ADC_CTRL_START_SINGLE		BIT(1)
37 #define XEC_ADC_CTRL_ACTIVATE			BIT(0)
38 
39 /* ADC implements two interrupt signals:
40  * One-shot(single) conversion of a set of channels
41  * Repeat conversion of a set of channels
42  * Channel sets for single and repeat may be different.
43  */
44 enum adc_pm_policy_state_flag {
45 	ADC_PM_POLICY_STATE_SINGLE_FLAG,
46 	ADC_PM_POLICY_STATE_REPEAT_FLAG,
47 	ADC_PM_POLICY_STATE_FLAG_COUNT,
48 };
49 
50 #define XEC_ADC_MAX_HW_CHAN 16
51 #define XEC_ADC_CFG_CHANNELS DT_INST_PROP(0, channels)
52 
53 struct adc_xec_regs {
54 	uint32_t control_reg;
55 	uint32_t delay_reg;
56 	uint32_t status_reg;
57 	uint32_t single_reg;
58 	uint32_t repeat_reg;
59 	uint32_t channel_read_reg[XEC_ADC_CFG_CHANNELS];
60 	uint32_t unused[10 + (XEC_ADC_MAX_HW_CHAN - XEC_ADC_CFG_CHANNELS)];
61 	uint32_t config_reg;
62 	uint32_t vref_channel_reg;
63 	uint32_t vref_control_reg;
64 	uint32_t sar_control_reg;
65 };
66 
67 struct adc_xec_config {
68 	struct adc_xec_regs *regs;
69 
70 	uint8_t girq_single;
71 	uint8_t girq_single_pos;
72 	uint8_t girq_repeat;
73 	uint8_t girq_repeat_pos;
74 	uint8_t pcr_regidx;
75 	uint8_t pcr_bitpos;
76 	const struct pinctrl_dev_config *pcfg;
77 };
78 
79 struct adc_xec_data {
80 	struct adc_context ctx;
81 	const struct device *adc_dev;
82 	uint16_t *buffer;
83 	uint16_t *repeat_buffer;
84 #ifdef CONFIG_PM_DEVICE
85 	ATOMIC_DEFINE(pm_policy_state_flag, ADC_PM_POLICY_STATE_FLAG_COUNT);
86 #endif
87 };
88 
89 #ifdef CONFIG_PM_DEVICE
adc_xec_pm_policy_state_lock_get(struct adc_xec_data * data,enum adc_pm_policy_state_flag flag)90 static void adc_xec_pm_policy_state_lock_get(struct adc_xec_data *data,
91 					       enum adc_pm_policy_state_flag flag)
92 {
93 	if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
94 		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
95 	}
96 }
97 
adc_xec_pm_policy_state_lock_put(struct adc_xec_data * data,enum adc_pm_policy_state_flag flag)98 static void adc_xec_pm_policy_state_lock_put(struct adc_xec_data *data,
99 					    enum adc_pm_policy_state_flag flag)
100 {
101 	if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
102 		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
103 	}
104 }
105 #endif
106 
adc_context_start_sampling(struct adc_context * ctx)107 static void adc_context_start_sampling(struct adc_context *ctx)
108 {
109 	struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
110 	const struct device *adc_dev = data->adc_dev;
111 	const struct adc_xec_config * const devcfg = adc_dev->config;
112 	struct adc_xec_regs *regs = devcfg->regs;
113 
114 	data->repeat_buffer = data->buffer;
115 
116 #ifdef CONFIG_PM_DEVICE
117 	adc_xec_pm_policy_state_lock_get(data, ADC_PM_POLICY_STATE_SINGLE_FLAG);
118 #endif
119 	regs->single_reg = ctx->sequence.channels;
120 	regs->control_reg |= XEC_ADC_CTRL_START_SINGLE;
121 }
122 
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)123 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
124 					      bool repeat_sampling)
125 {
126 	struct adc_xec_data *data = CONTAINER_OF(ctx, struct adc_xec_data, ctx);
127 
128 	if (repeat_sampling) {
129 		data->buffer = data->repeat_buffer;
130 	}
131 }
132 
adc_xec_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)133 static int adc_xec_channel_setup(const struct device *dev,
134 				 const struct adc_channel_cfg *channel_cfg)
135 {
136 	const struct adc_xec_config *const cfg = dev->config;
137 	struct adc_xec_regs * const regs = cfg->regs;
138 	uint32_t areg;
139 
140 	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
141 		return -EINVAL;
142 	}
143 
144 	if (channel_cfg->channel_id >= XEC_ADC_CFG_CHANNELS) {
145 		return -EINVAL;
146 	}
147 
148 	if (channel_cfg->gain != ADC_GAIN_1) {
149 		return -EINVAL;
150 	}
151 
152 	/* Setup VREF */
153 	areg = regs->vref_channel_reg;
154 	areg &= ~MCHP_ADC_CH_VREF_SEL_MASK(channel_cfg->channel_id);
155 
156 	if (channel_cfg->reference == ADC_REF_INTERNAL) {
157 		areg |= MCHP_ADC_CH_VREF_SEL_PAD(channel_cfg->channel_id);
158 	} else if (channel_cfg->reference == ADC_REF_EXTERNAL0) {
159 		areg |= MCHP_ADC_CH_VREF_SEL_GPIO(channel_cfg->channel_id);
160 	} else {
161 		return -EINVAL;
162 	}
163 
164 	regs->vref_channel_reg = areg;
165 
166 	/* Differential mode? */
167 	areg = regs->sar_control_reg;
168 	areg &= ~BIT(MCHP_ADC_SAR_CTRL_SELDIFF_POS);
169 	if (channel_cfg->differential != 0) {
170 		areg |= MCHP_ADC_SAR_CTRL_SELDIFF_EN;
171 	}
172 	regs->sar_control_reg = areg;
173 
174 	return 0;
175 }
176 
adc_xec_validate_buffer_size(const struct adc_sequence * sequence)177 static bool adc_xec_validate_buffer_size(const struct adc_sequence *sequence)
178 {
179 	int chan_count = 0;
180 	size_t buff_need;
181 	uint32_t chan_mask;
182 
183 	for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
184 		if (chan_mask & sequence->channels) {
185 			chan_count++;
186 		}
187 	}
188 
189 	buff_need = chan_count * sizeof(uint16_t);
190 
191 	if (sequence->options) {
192 		buff_need *= 1 + sequence->options->extra_samplings;
193 	}
194 
195 	if (buff_need > sequence->buffer_size) {
196 		return false;
197 	}
198 
199 	return true;
200 }
201 
adc_xec_start_read(const struct device * dev,const struct adc_sequence * sequence)202 static int adc_xec_start_read(const struct device *dev,
203 			      const struct adc_sequence *sequence)
204 {
205 	const struct adc_xec_config *const cfg = dev->config;
206 	struct adc_xec_regs * const regs = cfg->regs;
207 	struct adc_xec_data * const data = dev->data;
208 	uint32_t sar_ctrl;
209 
210 	if (sequence->channels & ~BIT_MASK(XEC_ADC_CFG_CHANNELS)) {
211 		LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
212 		return -EINVAL;
213 	}
214 
215 	if (sequence->channels == 0UL) {
216 		LOG_ERR("No channel selected");
217 		return -EINVAL;
218 	}
219 
220 	if (!adc_xec_validate_buffer_size(sequence)) {
221 		LOG_ERR("Incorrect buffer size");
222 		return -ENOMEM;
223 	}
224 
225 	/* Setup ADC resolution */
226 	sar_ctrl = regs->sar_control_reg;
227 	sar_ctrl &= ~(MCHP_ADC_SAR_CTRL_RES_MASK |
228 		      (1 << MCHP_ADC_SAR_CTRL_SHIFTD_POS));
229 
230 	if (sequence->resolution == 12) {
231 		sar_ctrl |= MCHP_ADC_SAR_CTRL_RES_12_BITS;
232 	} else if (sequence->resolution == 10) {
233 		sar_ctrl |= MCHP_ADC_SAR_CTRL_RES_10_BITS;
234 		sar_ctrl |= MCHP_ADC_SAR_CTRL_SHIFTD_EN;
235 	} else {
236 		return -EINVAL;
237 	}
238 
239 	regs->sar_control_reg = sar_ctrl;
240 
241 	data->buffer = sequence->buffer;
242 
243 	adc_context_start_read(&data->ctx, sequence);
244 
245 	return adc_context_wait_for_completion(&data->ctx);
246 }
247 
adc_xec_read(const struct device * dev,const struct adc_sequence * sequence)248 static int adc_xec_read(const struct device *dev,
249 			const struct adc_sequence *sequence)
250 {
251 	struct adc_xec_data * const data = dev->data;
252 	int error;
253 
254 	adc_context_lock(&data->ctx, false, NULL);
255 	error = adc_xec_start_read(dev, sequence);
256 	adc_context_release(&data->ctx, error);
257 
258 	return error;
259 }
260 
261 #ifdef CONFIG_ADC_ASYNC
adc_xec_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)262 static int adc_xec_read_async(const struct device *dev,
263 			      const struct adc_sequence *sequence,
264 			      struct k_poll_signal *async)
265 {
266 	struct adc_xec_data * const data = dev->data;
267 	int error;
268 
269 	adc_context_lock(&data->ctx, true, async);
270 	error = adc_xec_start_read(dev, sequence);
271 	adc_context_release(&data->ctx, error);
272 
273 	return error;
274 }
275 #endif /* CONFIG_ADC_ASYNC */
276 
xec_adc_get_sample(const struct device * dev)277 static void xec_adc_get_sample(const struct device *dev)
278 {
279 	const struct adc_xec_config *const cfg = dev->config;
280 	struct adc_xec_regs * const regs = cfg->regs;
281 	struct adc_xec_data * const data = dev->data;
282 	uint32_t idx;
283 	uint32_t channels = regs->status_reg;
284 	uint32_t ch_status = channels;
285 	uint32_t bit;
286 
287 	/*
288 	 * Using the enabled channel bit set, from
289 	 * lowest channel number to highest, find out
290 	 * which channel is enabled and copy the ADC
291 	 * values from hardware registers to the data
292 	 * buffer.
293 	 */
294 	bit = find_lsb_set(channels);
295 	while (bit != 0) {
296 		idx = bit - 1;
297 
298 		*data->buffer = (uint16_t)regs->channel_read_reg[idx];
299 		data->buffer++;
300 
301 		channels &= ~BIT(idx);
302 		bit = find_lsb_set(channels);
303 	}
304 
305 	/* Clear the status register */
306 	regs->status_reg = ch_status;
307 }
308 
309 #ifdef CONFIG_SOC_SERIES_MEC172X
adc_xec_girq_clr(uint8_t girq_idx,uint8_t girq_posn)310 static inline void adc_xec_girq_clr(uint8_t girq_idx, uint8_t girq_posn)
311 {
312 	mchp_xec_ecia_girq_src_clr(girq_idx, girq_posn);
313 }
314 
adc_xec_girq_en(uint8_t girq_idx,uint8_t girq_posn)315 static inline void adc_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
316 {
317 	mchp_xec_ecia_girq_src_en(girq_idx, girq_posn);
318 }
319 
adc_xec_girq_dis(uint8_t girq_idx,uint8_t girq_posn)320 static inline void adc_xec_girq_dis(uint8_t girq_idx, uint8_t girq_posn)
321 {
322 	mchp_xec_ecia_girq_src_dis(girq_idx, girq_posn);
323 }
324 #else
325 
adc_xec_girq_clr(uint8_t girq_idx,uint8_t girq_posn)326 static inline void adc_xec_girq_clr(uint8_t girq_idx, uint8_t girq_posn)
327 {
328 	MCHP_GIRQ_SRC(girq_idx) = BIT(girq_posn);
329 }
330 
adc_xec_girq_en(uint8_t girq_idx,uint8_t girq_posn)331 static inline void adc_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
332 {
333 	MCHP_GIRQ_ENSET(girq_idx) = BIT(girq_posn);
334 }
335 
adc_xec_girq_dis(uint8_t girq_idx,uint8_t girq_posn)336 static inline void adc_xec_girq_dis(uint8_t girq_idx, uint8_t girq_posn)
337 {
338 	MCHP_GIRQ_ENCLR(girq_idx) = MCHP_KBC_IBF_GIRQ;
339 }
340 #endif
341 
adc_xec_single_isr(const struct device * dev)342 static void adc_xec_single_isr(const struct device *dev)
343 {
344 	const struct adc_xec_config *const cfg = dev->config;
345 	struct adc_xec_regs * const regs = cfg->regs;
346 	struct adc_xec_data * const data = dev->data;
347 	uint32_t ctrl;
348 
349 	/* Clear START_SINGLE bit and clear SINGLE_DONE_STATUS */
350 	ctrl = regs->control_reg;
351 	ctrl &= ~XEC_ADC_CTRL_START_SINGLE;
352 	ctrl |= XEC_ADC_CTRL_SINGLE_DONE_STATUS;
353 	regs->control_reg = ctrl;
354 
355 	/* Also clear GIRQ source status bit */
356 	adc_xec_girq_clr(cfg->girq_single, cfg->girq_single_pos);
357 
358 	xec_adc_get_sample(dev);
359 
360 #ifdef CONFIG_PM_DEVICE
361 	adc_xec_pm_policy_state_lock_put(data, ADC_PM_POLICY_STATE_SINGLE_FLAG);
362 #endif
363 
364 	adc_context_on_sampling_done(&data->ctx, dev);
365 
366 	LOG_DBG("ADC ISR triggered.");
367 }
368 
369 
370 #ifdef CONFIG_PM_DEVICE
adc_xec_pm_action(const struct device * dev,enum pm_device_action action)371 static int adc_xec_pm_action(const struct device *dev, enum pm_device_action action)
372 {
373 	const struct adc_xec_config *const devcfg = dev->config;
374 	struct adc_xec_regs * const adc_regs = devcfg->regs;
375 	int ret;
376 
377 	switch (action) {
378 	case PM_DEVICE_ACTION_RESUME:
379 		ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
380 		/* ADC activate  */
381 		adc_regs->control_reg |= XEC_ADC_CTRL_ACTIVATE;
382 		break;
383 	case PM_DEVICE_ACTION_SUSPEND:
384 		/* ADC deactivate  */
385 		adc_regs->control_reg &= ~(XEC_ADC_CTRL_ACTIVATE);
386 		/* If application does not want to turn off ADC pins it will
387 		 * not define pinctrl-1 for this node.
388 		 */
389 		ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP);
390 		if (ret == -ENOENT) { /* pinctrl-1 does not exist.  */
391 			ret = 0;
392 		}
393 		break;
394 	default:
395 		ret = -ENOTSUP;
396 	}
397 
398 	return ret;
399 }
400 #endif /* CONFIG_PM_DEVICE */
401 
402 static DEVICE_API(adc, adc_xec_api) = {
403 	.channel_setup = adc_xec_channel_setup,
404 	.read = adc_xec_read,
405 #if defined(CONFIG_ADC_ASYNC)
406 	.read_async = adc_xec_read_async,
407 #endif
408 	.ref_internal = XEC_ADC_VREF_ANALOG,
409 };
410 
411 /* ADC Config Register */
412 #define XEC_ADC_CFG_CLK_VAL(clk_time)	(		\
413 	(clk_time << MCHP_ADC_CFG_CLK_LO_TIME_POS) |	\
414 	(clk_time << MCHP_ADC_CFG_CLK_HI_TIME_POS))
415 
adc_xec_init(const struct device * dev)416 static int adc_xec_init(const struct device *dev)
417 {
418 	const struct adc_xec_config *const cfg = dev->config;
419 	struct adc_xec_regs * const regs = cfg->regs;
420 	struct adc_xec_data * const data = dev->data;
421 	int ret;
422 
423 	data->adc_dev = dev;
424 
425 	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
426 	if (ret != 0) {
427 		LOG_ERR("XEC ADC V2 pinctrl setup failed (%d)", ret);
428 		return ret;
429 	}
430 
431 	regs->config_reg = XEC_ADC_CFG_CLK_VAL(DT_INST_PROP(0, clktime));
432 
433 	regs->control_reg =  XEC_ADC_CTRL_ACTIVATE
434 		| XEC_ADC_CTRL_POWER_SAVER_DIS
435 		| XEC_ADC_CTRL_SINGLE_DONE_STATUS
436 		| XEC_ADC_CTRL_REPEAT_DONE_STATUS;
437 
438 	adc_xec_girq_dis(cfg->girq_repeat, cfg->girq_repeat_pos);
439 	adc_xec_girq_clr(cfg->girq_repeat, cfg->girq_repeat_pos);
440 	adc_xec_girq_dis(cfg->girq_single, cfg->girq_single_pos);
441 	adc_xec_girq_clr(cfg->girq_single, cfg->girq_single_pos);
442 	adc_xec_girq_en(cfg->girq_single, cfg->girq_single_pos);
443 
444 	IRQ_CONNECT(DT_INST_IRQN(0),
445 		    DT_INST_IRQ(0, priority),
446 		    adc_xec_single_isr, DEVICE_DT_INST_GET(0), 0);
447 	irq_enable(DT_INST_IRQN(0));
448 
449 	adc_context_unlock_unconditionally(&data->ctx);
450 
451 	return 0;
452 }
453 
454 PINCTRL_DT_INST_DEFINE(0);
455 
456 static struct adc_xec_config adc_xec_dev_cfg_0 = {
457 	.regs = (struct adc_xec_regs *)(DT_INST_REG_ADDR(0)),
458 	.girq_single = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 0)),
459 	.girq_single_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 1)),
460 	.girq_repeat = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 2)),
461 	.girq_repeat_pos = (uint8_t)(DT_INST_PROP_BY_IDX(0, girqs, 3)),
462 	.pcr_regidx = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 0)),
463 	.pcr_bitpos = (uint8_t)(DT_INST_PROP_BY_IDX(0, pcrs, 1)),
464 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
465 };
466 
467 static struct adc_xec_data adc_xec_dev_data_0 = {
468 	ADC_CONTEXT_INIT_TIMER(adc_xec_dev_data_0, ctx),
469 	ADC_CONTEXT_INIT_LOCK(adc_xec_dev_data_0, ctx),
470 	ADC_CONTEXT_INIT_SYNC(adc_xec_dev_data_0, ctx),
471 };
472 
473 PM_DEVICE_DT_INST_DEFINE(0, adc_xec_pm_action);
474 
475 DEVICE_DT_INST_DEFINE(0, adc_xec_init, PM_DEVICE_DT_INST_GET(0),
476 		    &adc_xec_dev_data_0, &adc_xec_dev_cfg_0,
477 		    PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY,
478 		    &adc_xec_api);
479