| /Zephyr-latest/soc/renesas/smartbond/da1469x/ |
| D | soc.c | 66 uint32_t region_size; in z_renesas_configure_cache() local
75 region_size = (uint32_t)&__rom_region_end - cache_start; in z_renesas_configure_cache()
86 if (region_size > MB(16)) { in z_renesas_configure_cache()
88 } else if (region_size > MB(8)) { in z_renesas_configure_cache()
90 } else if (region_size > MB(4)) { in z_renesas_configure_cache()
92 } else if (region_size > MB(2)) { in z_renesas_configure_cache()
94 } else if (region_size > MB(1)) { in z_renesas_configure_cache()
96 } else if (region_size > KB(512)) { in z_renesas_configure_cache()
98 } else if (region_size > KB(256)) { in z_renesas_configure_cache()
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| /Zephyr-latest/tests/application_development/code_relocation/ |
| D | linker_xtensa_qemu_sram2.ld | 26 #define MPU_ALIGN(region_size) \ argument
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| /Zephyr-latest/soc/andestech/ae350/ |
| D | linker.ld | 63 #define MPU_ALIGN(region_size) \ argument
65 . = ALIGN( 1 << LOG2CEIL(region_size))
67 #define MPU_ALIGN(region_size) \ argument
72 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
213 #define MPU_ALIGN(region_size) \ argument
215 . = ALIGN( 1 << LOG2CEIL(region_size))
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| /Zephyr-latest/include/zephyr/arch/arc/v2/ |
| D | linker.ld | 42 #define MPU_ALIGN(region_size) \ argument
44 . = ALIGN( 1 << LOG2CEIL(region_size))
46 #define MPU_ALIGN(region_size) \ argument
51 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
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| /Zephyr-latest/drivers/flash/ |
| D | flash_npcx_fiu_nor.c | 64 size_t region_size) in is_within_region() argument
67 (addr < (region_start + region_size)) && in is_within_region()
68 ((addr + size) <= (region_start + region_size))); in is_within_region()
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| /Zephyr-latest/include/zephyr/arch/riscv/common/ |
| D | linker.ld | 92 #define MPU_ALIGN(region_size) \ argument
94 . = ALIGN( 1 << LOG2CEIL(region_size))
96 #define MPU_ALIGN(region_size) \ argument
101 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | linker.ld | 56 #define MPU_ALIGN(region_size) \ argument
58 . = ALIGN( 1 << LOG2CEIL(region_size))
60 #define MPU_ALIGN(region_size) \ argument
65 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
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| /Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/scripts/ |
| D | linker.ld | 71 #define MPU_ALIGN(region_size) \ argument
73 . = ALIGN(1 << LOG2CEIL(region_size))
75 #define MPU_ALIGN(region_size) \ argument
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| /Zephyr-latest/samples/boards/intel/adsp/code_relocation/ |
| D | linker_xtensa_intel_adsp_cavs.ld | 49 #define MPU_ALIGN(region_size) \ argument
|
| /Zephyr-latest/soc/infineon/cat1b/cyw20829/ |
| D | linker.ld | 66 #define MPU_ALIGN(region_size) \ argument
68 . = ALIGN( 1 << LOG2CEIL(region_size))
70 #define MPU_ALIGN(region_size) \ argument
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| /Zephyr-latest/include/zephyr/arch/arm/cortex_m/scripts/ |
| D | linker.ld | 73 #define MPU_ALIGN(region_size) \ argument
75 . = ALIGN( 1 << LOG2CEIL(region_size))
77 #define MPU_ALIGN(region_size) \ argument
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| /Zephyr-latest/arch/x86/ |
| D | gen_mmu.py | 504 region_size = region_end - region_start
511 self.map(region_start_phys, region_start, region_size, flags, level)
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | linker.ld | 22 #define MPU_ALIGN(region_size) . = ALIGN(4) argument
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