Home
last modified time | relevance | path

Searched refs:region (Results 1 – 25 of 485) sorted by relevance

12345678910>>...20

/Zephyr-latest/soc/nordic/common/
Ddmm.c46 const struct dmm_region *region; member
57 static struct dmm_heap *dmm_heap_find(void *region) in dmm_heap_find() argument
63 if (dh->region->dt_addr == (uintptr_t)region) { in dmm_heap_find()
71 static bool is_region_cacheable(const struct dmm_region *region) in is_region_cacheable() argument
73 return (IS_ENABLED(CONFIG_DCACHE) && (region->dt_attr & DT_MEM_CACHEABLE)); in is_region_cacheable()
83 const struct dmm_region *region) in is_user_buffer_correctly_preallocated() argument
87 if (!is_buffer_within_region(addr, user_length, region->dt_addr, region->dt_size)) { in is_user_buffer_correctly_preallocated()
91 if (!is_region_cacheable(region)) { in is_user_buffer_correctly_preallocated()
96 if (IS_ALIGNED(addr, region->dt_align)) { in is_user_buffer_correctly_preallocated()
106 return ROUND_UP(dh->region->dt_allc, dh->region->dt_align); in dmm_heap_start_get()
[all …]
Ddmm.h105 int dmm_buffer_out_prepare(void *region, void const *user_buffer, size_t user_length,
118 int dmm_buffer_out_release(void *region, void *buffer_out);
142 int dmm_buffer_in_prepare(void *region, void *user_buffer, size_t user_length, void **buffer_in);
164 int dmm_buffer_in_release(void *region, void *user_buffer, size_t user_length, void *buffer_in);
178 static ALWAYS_INLINE int dmm_buffer_out_prepare(void *region, void const *user_buffer,
181 ARG_UNUSED(region);
187 static ALWAYS_INLINE int dmm_buffer_out_release(void *region, void *buffer_out)
189 ARG_UNUSED(region);
194 static ALWAYS_INLINE int dmm_buffer_in_prepare(void *region, void *user_buffer, size_t user_length,
197 ARG_UNUSED(region);
[all …]
/Zephyr-latest/tests/lib/devicetree/memory_region_flags/
Dapp.overlay11 compatible = "zephyr,memory-region";
13 zephyr,memory-region = "TEST_REGION_R";
14 zephyr,memory-region-flags = "r";
18 compatible = "zephyr,memory-region";
20 zephyr,memory-region = "TEST_REGION_NRWXAIL";
21 zephyr,memory-region-flags = "!rwxail";
25 compatible = "zephyr,memory-region";
27 zephyr,memory-region = "TEST_REGION_NO_FLAGS";
31 compatible = "zephyr,memory-region";
33 zephyr,memory-region = "TEST_REGION_NONE";
[all …]
/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr/src/
Dmain.c13 const struct mem_attr_region_t *region; in ZTEST() local
16 num_regions = mem_attr_get_regions(&region); in ZTEST()
23 if (region[idx].dt_size == 0x1000) { in ZTEST()
24 zassert_equal(region[idx].dt_addr, 0x10000000, "Wrong region address"); in ZTEST()
25 zassert_equal(region[idx].dt_size, 0x1000, "Wrong region size"); in ZTEST()
26 zassert_equal(region[idx].dt_attr, DT_MEM_ARM_MPU_FLASH | in ZTEST()
29 zassert_str_equal(region[idx].dt_name, in ZTEST()
32 zassert_equal(region[idx].dt_addr, 0x20000000, "Wrong region address"); in ZTEST()
33 zassert_equal(region[idx].dt_size, 0x2000, "Wrong region size"); in ZTEST()
34 zassert_equal(region[idx].dt_attr, DT_MEM_ARM_MPU_RAM_NOCACHE, in ZTEST()
[all …]
/Zephyr-latest/tests/lib/shared_multi_heap/src/
Dmain.c22 struct shared_multi_heap_region region; member
28 .region = { \
41 static void smh_reg_map(struct shared_multi_heap_region *region) in smh_reg_map() argument
46 mem_attr = (region->attr == SMH_REG_ATTR_CACHEABLE) ? K_MEM_CACHE_WB : K_MEM_CACHE_NONE; in smh_reg_map()
49 k_mem_map_phys_bare(&v_addr, region->addr, region->size, mem_attr); in smh_reg_map()
51 region->addr = (uintptr_t) v_addr; in smh_reg_map()
62 if ((uintptr_t) v_addr >= map[reg].region.addr && in get_region_map()
63 (uintptr_t) v_addr < map[reg].region.addr + map[reg].region.size) { in get_region_map()
108 if (reg_map->region.attr == DT_MEM_ARM_MPU_UNKNOWN) { in fill_multi_heap()
113 reg_map->region.attr = mpu_to_reg_attr(reg_map->region.attr); in fill_multi_heap()
[all …]
/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/boards/
Dqemu_cortex_m3.overlay7 compatible = "zephyr,memory-region", "mmio-sram";
9 zephyr,memory-region = "MEM_CACHEABLE";
14 compatible = "zephyr,memory-region", "mmio-sram";
16 zephyr,memory-region = "MEM_CACHEABLE_SW";
21 compatible = "zephyr,memory-region", "mmio-sram";
23 zephyr,memory-region = "MEM_NON_CACHEABLE_SW";
28 compatible = "zephyr,memory-region", "mmio-sram";
30 zephyr,memory-region = "MEM_DMA_SW";
35 compatible = "zephyr,memory-region", "mmio-sram";
37 zephyr,memory-region = "MEM_CACHEABLE_SW_BIG";
[all …]
/Zephyr-latest/modules/loramac-node/
DCMakeLists.txt32 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region
63 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/Region.c
64 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionCommon.c
67 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionEU868.c
70 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionBaseUS.c
71 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionUS915.c
74 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionCN779.c
77 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionEU433.c
80 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionBaseUS.c
81 ${ZEPHYR_LORAMAC_NODE_MODULE_DIR}/src/mac/region/RegionAU915.c
[all …]
/Zephyr-latest/tests/subsys/mem_mgmt/mem_attr_heap/src/
Dmain.c21 const struct mem_attr_region_t *region; in ZTEST() local
47 region = mem_attr_heap_get_region(block); in ZTEST()
48 zassert_equal(region->dt_addr, ADDR_MEM_CACHE_SW, in ZTEST()
61 region = mem_attr_heap_get_region(block); in ZTEST()
62 zassert_equal(region->dt_addr, ADDR_MEM_NON_CACHE_SW, in ZTEST()
75 region = mem_attr_heap_get_region(block); in ZTEST()
76 zassert_equal(region->dt_addr, ADDR_MEM_DMA_SW, in ZTEST()
89 region = mem_attr_heap_get_region(block); in ZTEST()
90 zassert_equal(region->dt_addr, ADDR_MEM_CACHE_DMA_SW, in ZTEST()
110 region = mem_attr_heap_get_region(block); in ZTEST()
[all …]
/Zephyr-latest/subsys/mem_mgmt/
Dmem_attr.c22 size_t mem_attr_get_regions(const struct mem_attr_region_t **region) in mem_attr_get_regions() argument
24 *region = mem_attr_region; in mem_attr_get_regions()
47 const struct mem_attr_region_t *region = &mem_attr_region[idx]; in mem_attr_check_buf() local
48 size_t region_end = region->dt_addr + region->dt_size; in mem_attr_check_buf()
51 if ((addr >= region->dt_addr) && (addr < region_end)) { in mem_attr_check_buf()
55 return (region->dt_attr & attr) == attr ? 0 : -EINVAL; in mem_attr_check_buf()
/Zephyr-latest/tests/lib/shared_multi_heap/boards/
Dmps2_an521_cpu0.overlay14 compatible = "zephyr,memory-region", "mmio-sram";
16 zephyr,memory-region = "SSRAM2_3";
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES0";
27 compatible = "zephyr,memory-region", "mmio-sram";
29 zephyr,memory-region = "RES1";
34 compatible = "zephyr,memory-region", "mmio-sram";
36 zephyr,memory-region = "RES2";
Dqemu_cortex_a53.overlay13 compatible = "zephyr,memory-region", "mmio-sram";
15 zephyr,memory-region = "RES0";
20 compatible = "zephyr,memory-region", "mmio-sram";
22 zephyr,memory-region = "RES1";
27 compatible = "zephyr,memory-region", "mmio-sram";
29 zephyr,memory-region = "RES_NO_MPU";
33 compatible = "zephyr,memory-region", "mmio-sram";
35 zephyr,memory-region = "RES2";
/Zephyr-latest/dts/arm/st/h5/
Dstm32h533Xe.dtsi11 compatible = "zephyr,memory-region", "mmio-sram";
13 zephyr,memory-region = "SRAM1";
17 compatible = "zephyr,memory-region", "mmio-sram";
19 zephyr,memory-region = "SRAM2";
23 compatible = "zephyr,memory-region", "mmio-sram";
25 zephyr,memory-region = "SRAM3";
/Zephyr-latest/include/zephyr/drivers/
Dcoredump.h74 struct coredump_mem_region_node *region);
81 struct coredump_mem_region_node *region);
115 struct coredump_mem_region_node *region) in coredump_device_register_memory() argument
120 return api->register_memory(dev, region); in coredump_device_register_memory()
134 struct coredump_mem_region_node *region) in coredump_device_unregister_memory() argument
139 return api->unregister_memory(dev, region); in coredump_device_unregister_memory()
/Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/boards/
Dstm32h747i_disco_stm32h747xx_m7.overlay16 zephyr,memory-region = "SRAM_TX";
17 compatible = "zephyr,memory-region", "mmio-sram";
23 zephyr,memory-region = "SRAM_RX";
24 compatible = "zephyr,memory-region", "mmio-sram";
31 tx-region = <&sram_tx>;
32 rx-region = <&sram_rx>;
/Zephyr-latest/samples/subsys/ipc/ipc_service/icmsg/remote/boards/
Dstm32h747i_disco_stm32h747xx_m4.overlay19 zephyr,memory-region = "SRAM_RX";
20 compatible = "zephyr,memory-region", "mmio-sram";
26 zephyr,memory-region = "SRAM_TX";
27 compatible = "zephyr,memory-region", "mmio-sram";
34 tx-region = <&sram_tx>;
35 rx-region = <&sram_rx>;
/Zephyr-latest/dts/arm/st/h7/
Dstm32h743.dtsi74 compatible = "zephyr,memory-region", "mmio-sram";
75 zephyr,memory-region = "SRAM1";
80 compatible = "zephyr,memory-region", "mmio-sram";
82 zephyr,memory-region = "SRAM2";
87 compatible = "zephyr,memory-region", "mmio-sram";
89 zephyr,memory-region = "SRAM3";
95 compatible = "zephyr,memory-region", "mmio-sram";
96 zephyr,memory-region = "SRAM4";
100 compatible = "zephyr,memory-region", "arm,dtcm";
102 zephyr,memory-region = "DTCM";
[all …]
/Zephyr-latest/dts/arm/st/f7/
Dstm32f722.dtsi15 compatible = "zephyr,memory-region", "mmio-sram";
17 zephyr,memory-region = "SRAM0";
21 compatible = "zephyr,memory-region", "arm,dtcm";
23 zephyr,memory-region = "DTCM";
27 compatible = "zephyr,memory-region", "arm,itcm";
29 zephyr,memory-region = "ITCM";
/Zephyr-latest/dts/arm/st/u0/
Dstm32u031X4.dtsi12 compatible = "zephyr,memory-region", "mmio-sram";
14 zephyr,memory-region = "SRAM1";
18 compatible = "zephyr,memory-region", "mmio-sram";
20 zephyr,memory-region = "SRAM2";
Dstm32u031X6.dtsi12 compatible = "zephyr,memory-region", "mmio-sram";
14 zephyr,memory-region = "SRAM1";
18 compatible = "zephyr,memory-region", "mmio-sram";
20 zephyr,memory-region = "SRAM2";
Dstm32u031X8.dtsi12 compatible = "zephyr,memory-region", "mmio-sram";
14 zephyr,memory-region = "SRAM1";
18 compatible = "zephyr,memory-region", "mmio-sram";
20 zephyr,memory-region = "SRAM2";
Dstm32u083Xc.dtsi12 compatible = "zephyr,memory-region", "mmio-sram";
14 zephyr,memory-region = "SRAM1";
18 compatible = "zephyr,memory-region", "mmio-sram";
20 zephyr,memory-region = "SRAM2";
/Zephyr-latest/boards/arm/mps3/
Dmps3_corstone300_an547.dts65 compatible = "zephyr,memory-region";
67 zephyr,memory-region = "ITCM";
71 compatible = "zephyr,memory-region", "mmio-sram";
73 zephyr,memory-region = "SRAM";
77 compatible = "zephyr,memory-region";
79 zephyr,memory-region = "DTCM";
83 compatible = "zephyr,memory-region", "mmio-sram";
85 zephyr,memory-region = "ISRAM";
Dmps3_corstone300_an552.dts64 compatible = "zephyr,memory-region";
66 zephyr,memory-region = "ITCM";
70 compatible = "zephyr,memory-region", "mmio-sram";
72 zephyr,memory-region = "SRAM";
76 compatible = "zephyr,memory-region";
78 zephyr,memory-region = "DTCM";
82 compatible = "zephyr,memory-region", "mmio-sram";
84 zephyr,memory-region = "ISRAM";
Dmps3_corstone300_fvp.dts64 compatible = "zephyr,memory-region";
66 zephyr,memory-region = "ITCM";
70 compatible = "zephyr,memory-region", "mmio-sram";
72 zephyr,memory-region = "SRAM";
76 compatible = "zephyr,memory-region";
78 zephyr,memory-region = "DTCM";
82 compatible = "zephyr,memory-region", "mmio-sram";
84 zephyr,memory-region = "ISRAM";
Dmps3_corstone310_an555.dts64 compatible = "zephyr,memory-region";
66 zephyr,memory-region = "ITCM";
70 compatible = "zephyr,memory-region", "mmio-sram";
72 zephyr,memory-region = "SRAM";
76 compatible = "zephyr,memory-region";
78 zephyr,memory-region = "DTCM";
82 compatible = "zephyr,memory-region", "mmio-sram";
84 zephyr,memory-region = "ISRAM";

12345678910>>...20