Searched refs:q_idx (Results 1 – 2 of 2) sorted by relevance
336 uint32_t q_idx; in dwxgmac_dma_mtl_init() local361 for (q_idx = 0u; q_idx < max_q_count; q_idx++) { in dwxgmac_dma_mtl_init()371 ((q_idx / NUM_OF_RxQs_PER_DMA_MAP_REG) * XGMAC_REG_SIZE_BYTES)); in dwxgmac_dma_mtl_init()373 MTL_RXQ_DMA_MAP_Qx_MSK(q_idx % NUM_OF_RxQs_PER_DMA_MAP_REG)); in dwxgmac_dma_mtl_init()374 reg_val |= MTL_RXQ_DMA_MAP_QxDDMACH_SET((q_idx % NUM_OF_RxQs_PER_DMA_MAP_REG), in dwxgmac_dma_mtl_init()375 READ_BIT(tcq_config->rx_q_ddma_en, q_idx)) | in dwxgmac_dma_mtl_init()376 MTL_RXQ_DMA_MAP_QxMDMACH_SET((q_idx % NUM_OF_RxQs_PER_DMA_MAP_REG), in dwxgmac_dma_mtl_init()377 tcq_config->rx_q_dma_chnl_sel[q_idx]); in dwxgmac_dma_mtl_init()380 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()382 reg_val = MTL_TCQx_MTL_TXQx_OPERATION_MODE_TQS_SET(tcq_config->tx_q_size[q_idx]) | in dwxgmac_dma_mtl_init()[all …]
214 for (int q_idx = 0; q_idx < sample_idx; ++q_idx) { in sensor_submit_fallback_sync() local215 q[q_idx] = q[q_idx] >> (new_shift - header->shift); in sensor_submit_fallback_sync()
