Lines Matching refs:q_idx
336 uint32_t q_idx; in dwxgmac_dma_mtl_init() local
361 for (q_idx = 0u; q_idx < max_q_count; q_idx++) { in dwxgmac_dma_mtl_init()
371 ((q_idx / NUM_OF_RxQs_PER_DMA_MAP_REG) * XGMAC_REG_SIZE_BYTES)); in dwxgmac_dma_mtl_init()
373 MTL_RXQ_DMA_MAP_Qx_MSK(q_idx % NUM_OF_RxQs_PER_DMA_MAP_REG)); in dwxgmac_dma_mtl_init()
374 reg_val |= MTL_RXQ_DMA_MAP_QxDDMACH_SET((q_idx % NUM_OF_RxQs_PER_DMA_MAP_REG), in dwxgmac_dma_mtl_init()
375 READ_BIT(tcq_config->rx_q_ddma_en, q_idx)) | in dwxgmac_dma_mtl_init()
376 MTL_RXQ_DMA_MAP_QxMDMACH_SET((q_idx % NUM_OF_RxQs_PER_DMA_MAP_REG), in dwxgmac_dma_mtl_init()
377 tcq_config->rx_q_dma_chnl_sel[q_idx]); in dwxgmac_dma_mtl_init()
380 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()
382 reg_val = MTL_TCQx_MTL_TXQx_OPERATION_MODE_TQS_SET(tcq_config->tx_q_size[q_idx]) | in dwxgmac_dma_mtl_init()
384 tcq_config->q_to_tc_map[q_idx]) | in dwxgmac_dma_mtl_init()
385 MTL_TCQx_MTL_TXQx_OPERATION_MODE_TTC_SET(tcq_config->ttc[q_idx]) | in dwxgmac_dma_mtl_init()
388 READ_BIT(tcq_config->tsf_en, q_idx)); in dwxgmac_dma_mtl_init()
391 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()
393 reg_val = MTL_TCQx_MTC_TCx_ETS_CONTROL_TSA_SET(tcq_config->tsa[q_idx]); in dwxgmac_dma_mtl_init()
396 reg_addr = (ioaddr + XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(q_idx) + in dwxgmac_dma_mtl_init()
398 reg_val = MTL_TCQx_MTL_RXQx_OPERATION_MODE_RQS_SET(tcq_config->rx_q_size[q_idx]) | in dwxgmac_dma_mtl_init()
400 READ_BIT(tcq_config->hfc_en, q_idx)) | in dwxgmac_dma_mtl_init()
402 READ_BIT(tcq_config->cs_err_pkt_drop_dis, q_idx)) | in dwxgmac_dma_mtl_init()
404 READ_BIT(tcq_config->rsf_en, q_idx)) | in dwxgmac_dma_mtl_init()
406 READ_BIT(tcq_config->fep_en, q_idx)) | in dwxgmac_dma_mtl_init()
408 READ_BIT(tcq_config->fup_en, q_idx)) | in dwxgmac_dma_mtl_init()
409 MTL_TCQx_MTL_RXQx_OPERATION_MODE_RTC_SET(tcq_config->rtc[q_idx]); in dwxgmac_dma_mtl_init()