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Searched refs:pll_mul (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f0_f3.c26 uint32_t pll_source, pll_mul, pll_div; in config_pll_sysclock() local
36 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos); in config_pll_sysclock()
65 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div); in config_pll_sysclock()
76 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul); in config_pll_sysclock()
86 uint32_t pll_input_freq, pll_mul, pll_div; in get_pllout_frequency() local
96 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos); in get_pllout_frequency()
125 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul, pll_div); in get_pllout_frequency()
136 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul); in get_pllout_frequency()
Dclock_stm32f1.c47 uint32_t pll_source, pll_mul, pll_div; in config_pll_sysclock() local
63 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMULL_Pos); in config_pll_sysclock()
110 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul); in config_pll_sysclock()
129 uint32_t pll_mul, pll_div; in config_pll2() local
141 pll_mul = RCC_CFGR2_PLL2MUL20; in config_pll2()
143 pll_mul = ((STM32_PLL2_MULTIPLIER - 2) << RCC_CFGR2_PLL2MUL_Pos); in config_pll2()
160 LL_RCC_PLL_ConfigDomain_PLL2(pll_div, pll_mul); in config_pll2()
Dclock_stm32l0_l1.c23 #define pll_mul(v) z_pll_mul(v) macro
68 pll_mul(STM32_PLL_MULTIPLIER), in config_pll_sysclock()
79 pll_mul(STM32_PLL_MULTIPLIER), in get_pllout_frequency()