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Searched refs:pin (Results 1 – 25 of 1434) sorted by relevance

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/Zephyr-latest/tests/drivers/pinctrl/gd32/src/
Dmain_af.c17 pinctrl_soc_pin_t pin; in ZTEST() local
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_AF_GET(pin), GD32_AF0); in ZTEST()
30 zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE); in ZTEST()
31 zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP); in ZTEST()
32 zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ); in ZTEST()
34 pin = scfg->pins[1]; in ZTEST()
35 zassert_equal(GD32_PORT_GET(pin), 1); in ZTEST()
[all …]
Dmain_afio.c17 pinctrl_soc_pin_t pin; in ZTEST() local
26 pin = scfg->pins[0]; in ZTEST()
27 zassert_equal(GD32_PORT_GET(pin), 0); in ZTEST()
28 zassert_equal(GD32_PIN_GET(pin), 0); in ZTEST()
29 zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ANALOG); in ZTEST()
30 zassert_equal(GD32_REMAP_GET(pin), GD32_NORMP); in ZTEST()
32 pin = scfg->pins[1]; in ZTEST()
33 zassert_equal(GD32_PORT_GET(pin), 1); in ZTEST()
34 zassert_equal(GD32_PIN_GET(pin), 1); in ZTEST()
35 zassert_equal(GD32_MODE_GET(pin), GD32_MODE_ALTERNATE); in ZTEST()
[all …]
/Zephyr-latest/drivers/pinctrl/renesas/rz/
Dpinctrl_rzt2m.c21 #define DRCTL(port, pin) (PORT_NSR + 0xa00 + (0x8 * port) + pin) argument
32 #define PFC_FUNC_MASK(pin) (0xf << (pin * 4)) argument
34 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
36 uint8_t rselp = sys_read8(RSELP(pin->port)); in pinctrl_configure_pin()
37 uint32_t pfc = sys_read32(PFC(pin->port)) & ~(PFC_FUNC_MASK(pin->pin)); in pinctrl_configure_pin()
38 uint8_t pmc = sys_read8(PMC(pin->port)); in pinctrl_configure_pin()
41 sys_write8(rselp | BIT(pin->pin), RSELP(pin->port)); in pinctrl_configure_pin()
43 pin->drive_strength, (pin->pull_up == 1 ? 1U : (pin->pull_down == 1 ? 2U : 0)), in pinctrl_configure_pin()
44 pin->schmitt_enable, pin->slew_rate), in pinctrl_configure_pin()
45 DRCTL(pin->port, pin->pin)); in pinctrl_configure_pin()
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_numicro.c15 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
16 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
17 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
18 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
19 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
21 #define SLEWCTL_PIN_SHIFT(pin) ((pin) * 2) argument
22 #define SLEWCTL_MASK(pin) (3 << SLEWCTL_PIN_SHIFT(pin)) argument
26 #define REG_MFP(port, pin) (*(volatile uint32_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, mfp) + \ argument
28 ((pin) > 7 ? 4 : 0)))
[all …]
Dpinctrl_rpi_pico.c12 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
14 gpio_init(pin->pin_num); in pinctrl_configure_pin()
15 gpio_set_function(pin->pin_num, pin->alt_func); in pinctrl_configure_pin()
16 gpio_set_pulls(pin->pin_num, pin->pullup, pin->pulldown); in pinctrl_configure_pin()
17 gpio_set_drive_strength(pin->pin_num, pin->drive_strength); in pinctrl_configure_pin()
18 gpio_set_slew_rate(pin->pin_num, (pin->slew_rate ? in pinctrl_configure_pin()
20 gpio_set_input_hysteresis_enabled(pin->pin_num, pin->schmitt_enable); in pinctrl_configure_pin()
21 gpio_set_input_enabled(pin->pin_num, pin->input_enable); in pinctrl_configure_pin()
22 gpio_set_oeover(pin->pin_num, pin->oe_override); in pinctrl_configure_pin()
Dpinctrl_ambiq.c12 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
17 pin_config.uFuncSel = pin->alt_func; in pinctrl_configure_pin()
19 pin->input_enable ? AM_HAL_GPIO_PIN_INPUT_ENABLE : AM_HAL_GPIO_PIN_INPUT_NONE; in pinctrl_configure_pin()
20 pin_config.eGPOutcfg = pin->push_pull ? AM_HAL_GPIO_PIN_OUTCFG_PUSHPULL in pinctrl_configure_pin()
21 : pin->open_drain ? AM_HAL_GPIO_PIN_OUTCFG_OPENDRAIN in pinctrl_configure_pin()
22 : pin->tristate ? AM_HAL_GPIO_PIN_OUTCFG_TRISTATE in pinctrl_configure_pin()
24 pin_config.eDriveStrength = pin->drive_strength; in pinctrl_configure_pin()
25 pin_config.uNCE = pin->iom_nce; in pinctrl_configure_pin()
27 pin_config.bIomMSPIn = pin->iom_mspi; in pinctrl_configure_pin()
29 pin_config.uIOMnum = pin->iom_num; in pinctrl_configure_pin()
[all …]
Dpinctrl_eos_s3.c34 static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) in pinctrl_eos_s3_input_selection() argument
42 *reg = pin; in pinctrl_eos_s3_input_selection()
50 static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) in pinctrl_eos_s3_set() argument
54 if (pin > IO_MUX_REG_MAX_OFFSET) { in pinctrl_eos_s3_set()
57 reg += pin; in pinctrl_eos_s3_set()
63 static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_eos_s3_configure_pin() argument
68 reg_value |= (pin->iof & PAD_FUNC_SEL_MASK); in pinctrl_eos_s3_configure_pin()
71 WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1); in pinctrl_eos_s3_configure_pin()
74 WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable); in pinctrl_eos_s3_configure_pin()
75 WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate); in pinctrl_eos_s3_configure_pin()
[all …]
Dpinctrl_b91.c24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
43 #define reg_pin_mux(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, pin_mux) + \ argument
44 (((pin >> 8) < 4) ? ((pin >> 8) * 2) : 0) + \
45 (((pin >> 8) == 4) ? 0x20 : 0) + \
46 (((pin >> 8) == 5) ? 0x26 : 0) + \
47 ((pin & 0x0f0) ? 1 : 0)))
65 #define reg_pull_up_en(pin) ((uint8_t)(DT_INST_REG_ADDR_BY_NAME(0, pull_up_en) + \ argument
66 ((pin >> 8) * 2) + \
67 ((pin & 0xf0) ? 1 : 0)))
[all …]
Dpinctrl_nxp_s32.c31 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
36 __ASSERT_NO_MSG(pin->mscr.inst < ARRAY_SIZE(siul2_bases)); in pinctrl_configure_pin()
37 base = siul2_bases[pin->mscr.inst]; in pinctrl_configure_pin()
40 __ASSERT_NO_MSG(pin->mscr.idx < SIUL2_MSCR_MAX_IDX); in pinctrl_configure_pin()
41 sys_write32(pin->mscr.val, (base + SIUL2_MSCR(pin->mscr.idx))); in pinctrl_configure_pin()
44 if (pin->mscr.val & SIUL2_MSCR_IBE_MASK) { in pinctrl_configure_pin()
45 __ASSERT_NO_MSG(pin->imcr.inst < ARRAY_SIZE(siul2_bases)); in pinctrl_configure_pin()
46 base = siul2_bases[pin->imcr.inst]; in pinctrl_configure_pin()
49 __ASSERT_NO_MSG(pin->imcr.idx < SIUL2_IMCR_MAX_IDX); in pinctrl_configure_pin()
50 sys_write32(pin->imcr.val, (base + SIUL2_IMCR(pin->imcr.idx))); in pinctrl_configure_pin()
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_gpio.h116 void soc_gpio_configure(const struct soc_gpio_pin *pin);
140 static inline void soc_gpio_set(const struct soc_gpio_pin *pin) in soc_gpio_set() argument
143 pin->regs->OVRS = pin->mask; in soc_gpio_set()
145 pin->regs->PIO_SODR = pin->mask; in soc_gpio_set()
158 static inline void soc_gpio_clear(const struct soc_gpio_pin *pin) in soc_gpio_clear() argument
161 pin->regs->OVRC = pin->mask; in soc_gpio_clear()
163 pin->regs->PIO_CODR = pin->mask; in soc_gpio_clear()
176 static inline uint32_t soc_gpio_get(const struct soc_gpio_pin *pin) in soc_gpio_get() argument
179 return pin->regs->PVR & pin->mask; in soc_gpio_get()
181 return pin->regs->PIO_PDSR & pin->mask; in soc_gpio_get()
[all …]
/Zephyr-latest/boards/renesas/rcar_h3ulcb/
Drcar_h3ulcb_r8a77951_a57-pinctrl.dtsi11 pin = <PIN_TX2_A FUNC_TX2_A>;
15 pin = <PIN_RX2_A FUNC_RX2_A>;
19 pin = <PIN_SD0_CLK FUNC_SD0_CLK>;
24 pin = <PIN_SD0_CMD FUNC_SD0_CMD>;
29 pin = <PIN_SD0_DATA0 FUNC_SD0_DAT0>;
34 pin = <PIN_SD0_DATA1 FUNC_SD0_DAT1>;
39 pin = <PIN_SD0_DATA2 FUNC_SD0_DAT2>;
44 pin = <PIN_SD0_DATA3 FUNC_SD0_DAT3>;
49 pin = <PIN_SD0_CLK FUNC_SD0_CLK>;
54 pin = <PIN_SD0_CMD FUNC_SD0_CMD>;
[all …]
/Zephyr-latest/tests/drivers/sensor/adltc2990/boards/
Dnative_sim.overlay13 pin-v1-voltage-divider-resistors = <500 1000>;
14 pin-v2-voltage-divider-resistors = <110000 100000>;
15 pin-v3-voltage-divider-resistors = <7000 1000>;
16 pin-v4-voltage-divider-resistors = <500 1000>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
30 pin-v4-voltage-divider-resistors = <0 1>;
39 pin-v1-voltage-divider-resistors = <0 1>;
40 pin-v2-voltage-divider-resistors = <0 1>;
[all …]
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_port.c16 int soc_port_pinmux_set(PortGroup *pg, uint32_t pin, uint32_t func) in soc_port_pinmux_set() argument
18 bool is_odd = pin & 1; in soc_port_pinmux_set()
19 int idx = pin / 2U; in soc_port_pinmux_set()
30 pg->PINCFG[pin].bit.PMUXEN = 1; in soc_port_pinmux_set()
35 void soc_port_configure(const struct soc_port_pin *pin) in soc_port_configure() argument
37 PortGroup *pg = pin->regs; in soc_port_configure()
38 uint32_t flags = pin->flags; in soc_port_configure()
39 uint32_t func = (pin->flags & SOC_PORT_FUNC_MASK) >> SOC_PORT_FUNC_POS; in soc_port_configure()
43 pg->PINCFG[pin->pinum] = pincfg; in soc_port_configure()
44 pg->DIRCLR.reg = (1 << pin->pinum); in soc_port_configure()
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_numicro.c19 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
21 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
22 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
23 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
24 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
50 gpio_pin_t pin, gpio_flags_t flags) in gpio_numicro_configure() argument
103 regs->MODE = (regs->MODE & ~MODE_MASK(pin)) | in gpio_numicro_configure()
104 (mode << MODE_PIN_SHIFT(pin)); in gpio_numicro_configure()
105 regs->DBEN = (regs->DBEN & ~BIT(pin)) | (debounce_enable << pin); in gpio_numicro_configure()
[all …]
Dgpio_gd32.c43 #define EXTISS_LINE_SHIFT(pin) (EXTISS_STEP * ((pin) % EXTISS_STEP)) argument
82 gpio_pin_t pin) in gpio_gd32_configure_extiss() argument
88 switch (pin / EXTISS_STEP) { in gpio_gd32_configure_extiss()
121 shift = EXTISS_LINE_SHIFT(pin); in gpio_gd32_configure_extiss()
129 static inline int gpio_gd32_configure(const struct device *port, gpio_pin_t pin, in gpio_gd32_configure() argument
138 ctl &= ~GPIO_MODE_MASK(pin); in gpio_gd32_configure()
141 pupd &= ~GPIO_PUPD_MASK(pin); in gpio_gd32_configure()
144 ctl |= GPIO_MODE_SET(pin, GPIO_MODE_OUTPUT); in gpio_gd32_configure()
148 GPIO_OMODE(config->reg) |= BIT(pin); in gpio_gd32_configure()
153 GPIO_OMODE(config->reg) &= ~BIT(pin); in gpio_gd32_configure()
[all …]
Dgpio_ene_kb1200.c40 static int kb1200_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in kb1200_gpio_pin_configure() argument
44 WRITE_BIT(config->gpio_regs->GPIOFS, pin, 0); in kb1200_gpio_pin_configure()
46 WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1); in kb1200_gpio_pin_configure()
49 WRITE_BIT(config->gpio_regs->GPIOOD, pin, 1); in kb1200_gpio_pin_configure()
52 WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0); in kb1200_gpio_pin_configure()
55 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1); in kb1200_gpio_pin_configure()
57 WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0); in kb1200_gpio_pin_configure()
60 WRITE_BIT(config->gpio_regs->GPIOD, pin, 1); in kb1200_gpio_pin_configure()
62 WRITE_BIT(config->gpio_regs->GPIOD, pin, 0); in kb1200_gpio_pin_configure()
64 WRITE_BIT(config->gpio_regs->GPIOOE, pin, 1); in kb1200_gpio_pin_configure()
[all …]
Dgpio_rpi_pico.c37 gpio_pin_t pin, in gpio_rpi_configure() argument
42 gpio_set_pulls(pin, in gpio_rpi_configure()
47 gpio_set_function(pin, GPIO_FUNC_SIO); in gpio_rpi_configure()
51 data->single_ended_mask |= BIT(pin); in gpio_rpi_configure()
59 data->open_drain_mask |= BIT(pin); in gpio_rpi_configure()
60 gpio_put(pin, 0); in gpio_rpi_configure()
61 gpio_set_dir(pin, flags & GPIO_OUTPUT_INIT_LOW); in gpio_rpi_configure()
63 data->open_drain_mask &= ~(BIT(pin)); in gpio_rpi_configure()
64 gpio_put(pin, 1); in gpio_rpi_configure()
65 gpio_set_dir(pin, flags & GPIO_OUTPUT_INIT_HIGH); in gpio_rpi_configure()
[all …]
/Zephyr-latest/drivers/pinctrl/renesas/smartbond/
Dpinctrl_smartbond.c25 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin) in pinctrl_configure_pin() argument
30 __ASSERT_NO_MSG(pin->port < ARRAY_SIZE(smartbond_gpio_ports)); in pinctrl_configure_pin()
31 __ASSERT_NO_MSG(pin->pin < smartbond_gpio_ports[pin->port].pin_count); in pinctrl_configure_pin()
33 reg = (volatile uint32_t *)smartbond_gpio_ports[pin->port].p0_mode_addr; in pinctrl_configure_pin()
34 reg += pin->pin; in pinctrl_configure_pin()
36 reg_val = pin->func << GPIO_P0_00_MODE_REG_PID_Pos; in pinctrl_configure_pin()
37 if (pin->bias_pull_up) { in pinctrl_configure_pin()
39 } else if (pin->bias_pull_down) { in pinctrl_configure_pin()
41 } else if (pin->output_enable) { in pinctrl_configure_pin()
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c70 uint16_t pin, bool peripheral) in pfc_rcar_set_gpsr() argument
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr()
79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr()
103 static uint32_t pfc_rcar_get_drive_reg(uint16_t pin, uint8_t *offset, in pfc_rcar_get_drive_reg() argument
110 if (drive_regs->fields[i].pin == pin) { in pfc_rcar_get_drive_reg()
127 static int pfc_rcar_set_drive_strength(uintptr_t pfc_base, uint16_t pin, in pfc_rcar_set_drive_strength() argument
133 reg = pfc_rcar_get_drive_reg(pin, &offset, &size); in pfc_rcar_set_drive_strength()
157 static const struct pfc_bias_reg *pfc_rcar_get_bias_reg(uint16_t pin, in pfc_rcar_get_bias_reg() argument
165 if (bias_regs->pins[i] == pin) { in pfc_rcar_get_bias_reg()
176 int pfc_rcar_set_bias(uintptr_t pfc_base, uint16_t pin, uint16_t flags) in pfc_rcar_set_bias() argument
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nxp_pint.c25 uint8_t pin: 6; member
37 #define PIN_TO_INPUT_MUX_CONNECTION(pin) \ argument
38 ((PINTSEL_PMUX_ID << PMUX_SHIFT) + (pin))
41 static void attach_pin_to_pint(uint8_t pin, uint8_t pint_slot) in attach_pin_to_pint() argument
49 PIN_TO_INPUT_MUX_CONNECTION(pin)); in attach_pin_to_pint()
66 int nxp_pint_pin_enable(uint8_t pin, enum nxp_pint_trigger trigger, bool wake) in nxp_pint_pin_enable() argument
70 if (pin > ARRAY_SIZE(pin_pint_id)) { in nxp_pint_pin_enable()
75 if (pin_pint_id[pin] != NO_PINT_ID) { in nxp_pint_pin_enable()
76 slot = pin_pint_id[pin]; in nxp_pint_pin_enable()
87 pin_pint_id[pin] = slot; in nxp_pint_pin_enable()
[all …]
/Zephyr-latest/boards/renesas/rcar_salvator_xs/
Drcar_salvator_xs-pinctrl.dtsi11 pin = <PIN_TX2_A FUNC_TX2_A>;
15 pin = <PIN_RX2_A FUNC_RX2_A>;
19 pin = <PIN_SD2_CLK FUNC_SD2_CLK>;
24 pin = <PIN_SD2_CMD FUNC_SD2_CMD>;
29 pin = <PIN_SD2_DATA0 FUNC_SD2_DAT0>;
34 pin = <PIN_SD2_DATA1 FUNC_SD2_DAT1>;
39 pin = <PIN_SD2_DATA2 FUNC_SD2_DAT2>;
44 pin = <PIN_SD2_DATA3 FUNC_SD2_DAT3>;
49 pin = <PIN_SD1_DATA0 FUNC_SD2_DAT4>;
54 pin = <PIN_SD1_DATA1 FUNC_SD2_DAT5>;
[all …]
/Zephyr-latest/boards/renesas/rcar_spider_s4/
Drcar_spider_s4_r8a779f0_a55-pinctrl.dtsi11 pin = <PIN_HTX0 FUNC_HTX0>;
15 pin = <PIN_HRX0 FUNC_HRX0>;
19 pin = <PIN_MMC_SD_CLK FUNC_MMC_SD_CLK>;
24 pin = <PIN_MMC_SD_CMD FUNC_MMC_SD_CMD>;
29 pin = <PIN_MMC_SD_D0 FUNC_MMC_SD_D0>;
34 pin = <PIN_MMC_SD_D1 FUNC_MMC_SD_D1>;
39 pin = <PIN_MMC_SD_D2 FUNC_MMC_SD_D2>;
44 pin = <PIN_MMC_SD_D3 FUNC_MMC_SD_D3>;
49 pin = <PIN_MMC_D4 FUNC_MMC_D4>;
54 pin = <PIN_MMC_D5 FUNC_MMC_D5>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-ra-common.h25 #define RA_PINCFG(port, pin, psel, opt) \ argument
26 ((((psel)&PSEL_MASK) << PSEL_POS) | (((pin)&PIN_MASK) << PIN_POS) | \
31 #define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
35 #define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
39 #define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
43 #define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt) argument
/Zephyr-latest/include/zephyr/drivers/misc/timeaware_gpio/
Dtimeaware_gpio.h53 int (*pin_disable)(const struct device *dev, uint32_t pin);
56 int (*set_perout)(const struct device *dev, uint32_t pin, uint64_t start_time,
58 int (*config_ext_ts)(const struct device *dev, uint32_t pin, uint32_t event_polarity);
59 int (*read_ts_ec)(const struct device *dev, uint32_t pin, uint64_t *timestamp,
111 __syscall int tgpio_pin_disable(const struct device *dev, uint32_t pin);
113 static inline int z_impl_tgpio_pin_disable(const struct device *dev, uint32_t pin) in z_impl_tgpio_pin_disable() argument
117 return api->pin_disable(dev, pin); in z_impl_tgpio_pin_disable()
129 __syscall int tgpio_pin_config_ext_timestamp(const struct device *dev, uint32_t pin,
132 static inline int z_impl_tgpio_pin_config_ext_timestamp(const struct device *dev, uint32_t pin, in z_impl_tgpio_pin_config_ext_timestamp() argument
137 return api->config_ext_ts(dev, pin, event_polarity); in z_impl_tgpio_pin_config_ext_timestamp()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/
Dxg21-pinctrl.h16 #define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) argument
18 #define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1) argument
20 #define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2) argument
21 #define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3) argument
22 #define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4) argument
23 #define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) argument
25 #define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1) argument
26 #define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 17, 1, 1, 2) argument
27 #define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 17, 1, 2, 3) argument
29 #define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1) argument
[all …]

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