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Searched refs:phy_addr (Results 1 – 18 of 18) sorted by relevance

/Zephyr-latest/drivers/ethernet/
Dphy_xlnx_gem.c37 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_read() argument
61 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_read()
72 reg_val |= (((uint32_t)phy_addr & ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK) << in phy_xlnx_gem_mdio_read()
94 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_read()
116 uint32_t base_addr, uint8_t phy_addr, in phy_xlnx_gem_mdio_write() argument
140 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_write()
151 reg_val |= (((uint32_t)phy_addr & ETH_XLNX_GEM_PHY_MAINT_PHY_ADDRESS_MASK) << in phy_xlnx_gem_mdio_write()
175 base_addr, phy_addr, reg_addr); in phy_xlnx_gem_mdio_write()
209 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
212 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
[all …]
Dphy_gecko.c54 static int mdio_bus_send(ETH_TypeDef *eth, uint8_t phy_addr, uint8_t reg_addr, in mdio_bus_send() argument
63 | ((phy_addr << _ETH_PHYMNGMNT_PHYADDR_SHIFT) in mdio_bus_send()
84 uint8_t phy_addr = phy->address; in phy_read() local
87 retval = mdio_bus_send(eth, phy_addr, reg_addr, 1, 0); in phy_read()
103 uint8_t phy_addr = phy->address; in phy_write() local
105 return mdio_bus_send(eth, phy_addr, reg_addr, 0, value); in phy_write()
Dphy_cyclonev.c100 uint16_t phy_addr; in alt_eth_phy_write_register() local
106 phy_addr = PHY_ADDR; in alt_eth_phy_write_register()
111 tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); in alt_eth_phy_write_register()
147 uint16_t phy_addr; in alt_eth_phy_read_register() local
153 phy_addr = PHY_ADDR; in alt_eth_phy_read_register()
158 tmpreg |= EMAC_GMAC_GMII_ADDR_PA_SET(phy_addr); in alt_eth_phy_read_register()
Deth_numaker.c47 uint32_t phy_addr; member
718 eth_phy_addr = cfg->phy_addr; in eth_numaker_init()
779 .phy_addr = DT_INST_PROP(0, phy_addr),
Deth_adin2111_priv.h263 const uint16_t phy_addr; member
Deth_xlnx_gem_priv.h483 .phy_addr = 0,\
751 uint8_t phy_addr; member
Deth_adin2111.c1165 cfg->phy_addr, cfg->port_idx); in adin2111_port_iface_init()
1523 #define ADIN2111_MDIO_PHY_BY_ADDR(adin_n, phy_addr) \ argument
1524 DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(adin_n, mdio), ethernet_phy_##phy_addr))
1537 .phy_addr = phy_n, \
/Zephyr-latest/drivers/ethernet/phy/
Dphy_adin2111.c93 uint8_t phy_addr; member
114 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_read()
122 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_write()
131 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad); in phy_adin2111_c45_setup_dev_reg()
135 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, reg); in phy_adin2111_c45_setup_dev_reg()
140 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad | BIT(14)); in phy_adin2111_c45_setup_dev_reg()
156 return mdio_read(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_read()
159 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_read()
175 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_write()
178 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_write()
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Dphy_mii.c22 uint8_t phy_addr; member
56 return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_read()
68 return mdio_write(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_write()
171 LOG_INF("PHY (%d) is down", cfg->phy_addr); in update_link_state()
179 cfg->phy_addr); in update_link_state()
202 cfg->phy_addr); in update_link_state()
222 cfg->phy_addr); in update_link_state()
256 cfg->phy_addr, in update_link_state()
462 cfg->phy_addr); in phy_mii_initialize()
467 LOG_INF("PHY (%d) ID %X", cfg->phy_addr, phy_id); in phy_mii_initialize()
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Dphy_dm8806.c25 uint8_t phy_addr; member
328 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
335 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
343 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
350 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
358 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
366 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
374 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
381 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
451 .phy_addr = DT_INST_REG_ADDR(n), \
Dphy_tja1103.c60 uint8_t phy_addr; member
83 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja1103_c22_read()
90 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_tja1103_c22_write()
98 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_tja1103_c45_write()
106 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_tja1103_c45_read()
369 LOG_ERR("Unable to obtain PHY ID for device 0x%x", cfg->phy_addr); in phy_tja1103_init()
448 .phy_addr = DT_INST_REG_ADDR(n), \
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c51 static int mdio_xmc4xxx_transfer(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_transfer() argument
74 FIELD_PREP(ETH_GMII_ADDRESS_PA_Msk, phy_addr) | in mdio_xmc4xxx_transfer()
94 static int mdio_xmc4xxx_read(const struct device *dev, uint8_t phy_addr, uint8_t reg_addr, in mdio_xmc4xxx_read() argument
97 return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 0, 0, data); in mdio_xmc4xxx_read()
100 static int mdio_xmc4xxx_write(const struct device *dev, uint8_t phy_addr, in mdio_xmc4xxx_write() argument
103 return mdio_xmc4xxx_transfer(dev, phy_addr, reg_addr, 1, data, NULL); in mdio_xmc4xxx_write()
/Zephyr-latest/drivers/crypto/
Dcrypto_smartbond.c403 uint32_t phy_addr = black_orca_phy_addr((uint32_t)in_buf); in crypto_smartbond_set_in_out_buf() local
405 if (IS_QSPIF_CACHED_ADDRESS(phy_addr)) { in crypto_smartbond_set_in_out_buf()
410 phy_addr += (MCU_QSPIF_M_BASE - MCU_QSPIF_M_CACHED_BASE); in crypto_smartbond_set_in_out_buf()
411 } else if (IS_OTP_ADDRESS(phy_addr)) { in crypto_smartbond_set_in_out_buf()
413 phy_addr += (MCU_OTP_M_P_BASE - MCU_OTP_M_BASE); in crypto_smartbond_set_in_out_buf()
416 AES_HASH->CRYPTO_FETCH_ADDR_REG = phy_addr; in crypto_smartbond_set_in_out_buf()
/Zephyr-latest/drivers/ethernet/nxp_enet/
Deth_mcux.c184 uint32_t phy_addr; member
344 ENET_StartSMIWrite(context->base, context->phy_addr, in eth_mcux_phy_enter_reset()
366 context->phy_handle->phyAddr = context->phy_addr; in eth_mcux_phy_start()
370 ENET_StartSMIWrite(context->base, context->phy_addr, in eth_mcux_phy_start()
461 ENET_StartSMIWrite(context->base, context->phy_addr, in eth_mcux_phy_event()
492 ENET_StartSMIWrite(context->base, context->phy_addr, in eth_mcux_phy_event()
509 ENET_StartSMIWrite(context->base, context->phy_addr, in eth_mcux_phy_event()
524 ENET_StartSMIRead(context->base, context->phy_addr, in eth_mcux_phy_event()
544 ENET_StartSMIRead(context->base, context->phy_addr, in eth_mcux_phy_event()
1514 .phy_addr = DT_INST_PROP(n, phy_addr), \
/Zephyr-latest/drivers/i2c/
Di2c_dw.h124 uintptr_t phy_addr; member
Di2c_dw.c101 return (void *)(dw->phy_addr + DW_IC_REG_DATA_CMD); in i2c_dw_dr_phy_addr()
1077 dw->phy_addr = mbar.phys_addr; in i2c_dw_initialize()
1079 sys_write32((uint32_t)dw->phy_addr, in i2c_dw_initialize()
1081 sys_write32((uint32_t)(dw->phy_addr >> DMA_INTEL_LPSS_ADDR_RIGHT_SHIFT), in i2c_dw_initialize()
1083 LOG_DBG("i2c instance physical addr: [0x%lx], virtual addr: [0x%lx]", dw->phy_addr, in i2c_dw_initialize()
/Zephyr-latest/subsys/net/lib/ptp/
Dtlv.h201 uint8_t *phy_addr; member
Dtlv.c110 clock_desc->phy_addr = data; in tlv_mgmt_post_recv()