Searched refs:mstp (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_renesas_ra_cgc.c | 33 WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, false); in clock_control_renesas_ra_on()
45 WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, true); in clock_control_renesas_ra_off()
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| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | renesas_ra_cgc.h | 77 uint32_t mstp; member
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| /Zephyr-latest/drivers/can/ |
| D | can_renesas_ra.c | 1028 .op_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(
1029 DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk, mstp),
1033 .ram_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(
1035 mstp),
1111 .mstp = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, mstp), \
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| /Zephyr-latest/drivers/mipi_dsi/ |
| D | dsi_renesas_ra.c | 303 .clock_dsi_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp), \
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| /Zephyr-latest/drivers/display/ |
| D | display_renesas_ra.c | 425 .clock_glcdc_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp), \
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| /Zephyr-latest/drivers/pwm/ |
| D | pwm_renesas_ra.c | 556 .mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(index, 0, mstp), \
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| /Zephyr-latest/drivers/serial/ |
| D | uart_renesas_ra.c | 665 .mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp), \
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| /Zephyr-latest/drivers/spi/ |
| D | spi_b_renesas_ra8.c | 734 .mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_NAME(index, spiclk, \
735 mstp), \
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