Searched refs:l1_page_table (Results 1 – 2 of 2) sorted by relevance
41 l1_page_table __aligned(KB(16)) = {0};412 __ASSERT(l1_page_table.entries[l1_index].undefined.id == ARM_MMU_PTE_ID_INVALID, in arm_mmu_l1_map_section()414 l1_page_table.entries[l1_index].undefined.id, in arm_mmu_l1_map_section()417 l1_page_table.entries[l1_index].l1_section_1m.id = in arm_mmu_l1_map_section()419 l1_page_table.entries[l1_index].l1_section_1m.bufferable = perms_attrs.bufferable; in arm_mmu_l1_map_section()420 l1_page_table.entries[l1_index].l1_section_1m.cacheable = perms_attrs.cacheable; in arm_mmu_l1_map_section()421 l1_page_table.entries[l1_index].l1_section_1m.exec_never = perms_attrs.exec_never; in arm_mmu_l1_map_section()422 l1_page_table.entries[l1_index].l1_section_1m.domain = perms_attrs.domain; in arm_mmu_l1_map_section()423 l1_page_table.entries[l1_index].l1_section_1m.impl_def = 0; in arm_mmu_l1_map_section()424 l1_page_table.entries[l1_index].l1_section_1m.acc_perms10 = in arm_mmu_l1_map_section()[all …]
56 static uint32_t l1_page_table[CONFIG_XTENSA_MMU_NUM_L1_TABLES][XTENSA_L1_PAGE_TABLE_ENTRIES] variable63 uint32_t *xtensa_kernel_ptables = (uint32_t *)l1_page_table[0];297 map_memory_range((uint32_t) &l1_page_table[0], in xtensa_init_page_tables()298 (uint32_t) &l1_page_table[CONFIG_XTENSA_MMU_NUM_L1_TABLES], in xtensa_init_page_tables()676 sys_cache_data_invd_range((void *)l1_page_table, sizeof(l1_page_table)); in xtensa_mmu_tlb_shootdown()734 return (uint32_t *)&l1_page_table[idx]; in alloc_l1_table()
