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Searched refs:intr_status (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/drivers/dma/
Ddma_esp32_gdma.c81 struct dma_esp32_channel *rx, uint32_t intr_status) in dma_esp32_isr_handle_rx() argument
86 gdma_ll_rx_clear_interrupt_status(data->hal.dev, rx->channel_id, intr_status); in dma_esp32_isr_handle_rx()
88 if (intr_status == (GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_DONE)) { in dma_esp32_isr_handle_rx()
90 } else if (intr_status == GDMA_LL_EVENT_RX_DONE) { in dma_esp32_isr_handle_rx()
93 } else if (intr_status == GDMA_LL_EVENT_RX_WATER_MARK) { in dma_esp32_isr_handle_rx()
97 status = -intr_status; in dma_esp32_isr_handle_rx()
106 struct dma_esp32_channel *tx, uint32_t intr_status) in dma_esp32_isr_handle_tx() argument
110 gdma_ll_tx_clear_interrupt_status(data->hal.dev, tx->channel_id, intr_status); in dma_esp32_isr_handle_tx()
112 intr_status &= ~(GDMA_LL_EVENT_TX_TOTAL_EOF | GDMA_LL_EVENT_TX_DONE | GDMA_LL_EVENT_TX_EOF); in dma_esp32_isr_handle_tx()
115 tx->cb(dev, tx->user_data, tx->channel_id * 2 + 1, -intr_status); in dma_esp32_isr_handle_tx()
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_dw.c24 static ALWAYS_INLINE void dw_ictl_dispatch_child_isrs(uint32_t intr_status, in dw_ictl_dispatch_child_isrs() argument
30 while (intr_status) { in dw_ictl_dispatch_child_isrs()
31 intr_bitpos = find_lsb_set(intr_status) - 1; in dw_ictl_dispatch_child_isrs()
32 intr_status &= ~(1 << intr_bitpos); in dw_ictl_dispatch_child_isrs()
Dintc_cavs.c39 static ALWAYS_INLINE void cavs_ictl_dispatch_child_isrs(uint32_t intr_status, in cavs_ictl_dispatch_child_isrs() argument
45 while (intr_status) { in cavs_ictl_dispatch_child_isrs()
46 intr_bitpos = find_lsb_set(intr_status) - 1; in cavs_ictl_dispatch_child_isrs()
47 intr_status &= ~(1 << intr_bitpos); in cavs_ictl_dispatch_child_isrs()
/Zephyr-latest/drivers/spi/
Dspi_pw.c502 uint32_t intr_status; in spi_pw_transfer() local
505 intr_status = spi_pw_reg_read(dev, PW_SPI_REG_SSSR); in spi_pw_transfer()
507 if (intr_status & PW_SPI_SSSR_ROR_BIT) { in spi_pw_transfer()
513 if (intr_status & PW_SPI_SSSR_TUR_BIT) { in spi_pw_transfer()
519 if (intr_status & PW_SPI_SSSR_TINT_BIT) { in spi_pw_transfer()
527 if (intr_status & PW_SPI_SSSR_RNE_BIT) { in spi_pw_transfer()
531 if (intr_status & PW_SPI_SSSR_TNF_BIT) { in spi_pw_transfer()
Dspi_andes_atcspi200.c760 uint32_t i, dfs, intr_status, spi_status; in spi_atcspi200_irq_handler() local
764 intr_status = sys_read32(SPI_INTST(cfg->base)); in spi_atcspi200_irq_handler()
767 if ((intr_status & INTST_TX_FIFO_INT_MSK) && in spi_atcspi200_irq_handler()
768 !(intr_status & INTST_END_INT_MSK)) { in spi_atcspi200_irq_handler()
813 if (intr_status & INTST_RX_FIFO_INT_MSK) { in spi_atcspi200_irq_handler()
840 if (intr_status & INTST_END_INT_MSK) { in spi_atcspi200_irq_handler()
/Zephyr-latest/drivers/flash/
Dflash_andes_qspi.c731 uint32_t i, intr_status, spi_status; in qspi_andes_irq_handler() local
735 intr_status = sys_read32(QSPI_INTST(base)); in qspi_andes_irq_handler()
737 if ((intr_status & INTST_TX_FIFO_INT_MSK) && in qspi_andes_irq_handler()
738 !(intr_status & INTST_END_INT_MSK)) { in qspi_andes_irq_handler()
761 if (intr_status & INTST_RX_FIFO_INT_MSK) { in qspi_andes_irq_handler()
776 if (intr_status & INTST_END_INT_MSK) { in qspi_andes_irq_handler()
/Zephyr-latest/drivers/gpio/
Dgpio_eos_s3.c345 uint32_t intr_status = (INTR_CTRL->GPIO_INTR | INTR_CTRL->GPIO_INTR_RAW); in gpio_eos_s3_isr() local
348 INTR_CTRL->GPIO_INTR |= intr_status; in gpio_eos_s3_isr()