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/Zephyr-latest/doc/connectivity/bluetooth/img/
Datt_timeout.svg1 …g><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/><g/>…
/Zephyr-latest/doc/safety/images/
DIEC-61508-basis.svg1 …g[data-mml-node="merror"] &gt; g {&#xa; fill: red;&#xa; stroke: red;&#xa;}&#xa;&#xa;g[data-mml-n…
Dzephyr-safety-process.svg1 …g><path d="M 578 181 L 698 181 L 698 196 L 688 211 L 578 211 Z" fill="rgb(255, 255, 255)" stroke="…
/Zephyr-latest/boards/shields/nrf7002eb/
Dnrf7002eb.overlay33 wifi-max-tx-pwr-2g-dsss = <21>;
34 wifi-max-tx-pwr-2g-mcs0 = <16>;
35 wifi-max-tx-pwr-2g-mcs7 = <16>;
36 wifi-max-tx-pwr-5g-low-mcs0 = <13>;
37 wifi-max-tx-pwr-5g-low-mcs7 = <13>;
38 wifi-max-tx-pwr-5g-mid-mcs0 = <13>;
39 wifi-max-tx-pwr-5g-mid-mcs7 = <13>;
40 wifi-max-tx-pwr-5g-high-mcs0 = <12>;
41 wifi-max-tx-pwr-5g-high-mcs7 = <12>;
/Zephyr-latest/boards/shields/nrf7002ek/
Dnrf7002ek_common_5g.dtsi7 wifi-max-tx-pwr-5g-low-mcs0 = <13>;
8 wifi-max-tx-pwr-5g-low-mcs7 = <13>;
9 wifi-max-tx-pwr-5g-mid-mcs0 = <13>;
10 wifi-max-tx-pwr-5g-mid-mcs7 = <13>;
11 wifi-max-tx-pwr-5g-high-mcs0 = <12>;
12 wifi-max-tx-pwr-5g-high-mcs7 = <12>;
Dnrf7002ek_common.dtsi21 wifi-max-tx-pwr-2g-dsss = <21>;
22 wifi-max-tx-pwr-2g-mcs0 = <16>;
23 wifi-max-tx-pwr-2g-mcs7 = <16>;
/Zephyr-latest/boards/nordic/nrf7002dk/
Dnrf70_common_5g.dtsi7 wifi-max-tx-pwr-5g-low-mcs0 = <9>;
8 wifi-max-tx-pwr-5g-low-mcs7 = <9>;
9 wifi-max-tx-pwr-5g-mid-mcs0 = <11>;
10 wifi-max-tx-pwr-5g-mid-mcs7 = <11>;
11 wifi-max-tx-pwr-5g-high-mcs0 = <13>;
12 wifi-max-tx-pwr-5g-high-mcs7 = <13>;
Dnrf70_common.dtsi12 wifi-max-tx-pwr-2g-dsss = <21>;
13 wifi-max-tx-pwr-2g-mcs0 = <16>;
14 wifi-max-tx-pwr-2g-mcs7 = <16>;
/Zephyr-latest/drivers/interrupt_controller/
Dintc_ite_it8xxx2_v2.c17 #define IT8XXX2_INTC_BASE_SHIFT(g) (IT8XXX2_INTC_BASE + ((g) << 2)) argument
20 #define IT8XXX2_INTC_ISR(g) ECREG(IT8XXX2_INTC_BASE_SHIFT(g) + \ argument
21 ((g) < 4 ? 0x0 : 0x4))
23 #define IT8XXX2_INTC_IER(g) ECREG(IT8XXX2_INTC_BASE_SHIFT(g) + \ argument
24 ((g) < 4 ? 0x1 : 0x5))
26 #define IT8XXX2_INTC_IELMR(g) ECREG(IT8XXX2_INTC_BASE_SHIFT(g) + \ argument
27 ((g) < 4 ? 0x2 : 0x6))
29 #define IT8XXX2_INTC_IPOLR(g) ECREG(IT8XXX2_INTC_BASE_SHIFT(g) + \ argument
30 ((g) < 4 ? 0x3 : 0x7))
Dintc_ite_it8xxx2.c101 uint32_t g, i; in ite_intc_isr_clear() local
107 g = irq / MAX_REGISR_IRQ_NUM; in ite_intc_isr_clear()
109 isr = reg_status[g]; in ite_intc_isr_clear()
115 uint32_t g, i; in ite_intc_irq_enable() local
121 g = irq / MAX_REGISR_IRQ_NUM; in ite_intc_irq_enable()
123 en = reg_enable[g]; in ite_intc_irq_enable()
133 uint32_t g, i; in ite_intc_irq_disable() local
140 g = irq / MAX_REGISR_IRQ_NUM; in ite_intc_irq_disable()
142 en = reg_enable[g]; in ite_intc_irq_disable()
157 uint32_t g, i; in ite_intc_irq_polarity_set() local
[all …]
/Zephyr-latest/boards/intel/niosv_g/doc/
Dindex.rst9 niosv_g board is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system and t…
13 Nios® V/g Processor Intel® FPGA IP
17 Nios® V/g hello world example design system
20 Prebuilt Nios® V/g hello world example design system is available in Intel FPGA Design store.
23 For example, Arria10 Nios® V/g processor example design system prebuilt files can be downloaded fro…
24 …t/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html
28 Create Nios® V/g processor example design system in FPGA
31 Please use Intel Quartus Programmer tool to program Nios® V/g processor based system into the FPGA …
33 In order to create the Nios® V/g processor inside the FPGA device, please download the generated .s…
53 niosv-download -g <elf file>
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/Zephyr-latest/samples/drivers/led/lp5562/src/
Dmain.c68 static int set_static_color(const struct device *dev, uint8_t r, uint8_t g, in set_static_color() argument
74 g = scale_color_to_percent(g); in set_static_color()
83 ret = led_set_brightness(dev, LED_G, g); in set_static_color()
113 static int blink_color(const struct device *dev, bool r, bool g, bool b, in blink_color() argument
126 if (g) { in blink_color()
/Zephyr-latest/arch/common/
Dfill_with_zeros.ld9 * counter) in executable segments with TrapInstr pattern, e.g. for ARM the
13 * We may want to have some section (e.g. rom_start) filled with 0x00,
14 * e.g. because MCU can interpret the pattern as a configuration data.
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h19 #define MCHP_XEC_ECIA(g, gb, na, nd) \ argument
20 (((g) & 0x1f) + (((gb) & 0x1f) << 8) + (((na) & 0xff) << 16) + \
/Zephyr-latest/samples/drivers/video/capture/src/
Dcheck_test_pattern.h37 static inline CIELAB rgb888_to_lab(const uint8_t r, const uint8_t g, const uint8_t b) in rgb888_to_lab() argument
42 double g_lin = g / 255.0; in rgb888_to_lab()
70 uint8_t g = (color >> 8) & 0xFF; in xrgb32_to_lab() local
73 return rgb888_to_lab(r, g, b); in xrgb32_to_lab()
84 uint8_t g = (g6 * 255) / 63; in rgb565_to_lab() local
87 return rgb888_to_lab(r, g, b); in rgb565_to_lab()
/Zephyr-latest/doc/_extensions/zephyr/
Dapi_overview.py35 g
36 for g in all_groups
37 if g.get_compounddef()[0].get_id() == innergroup.get_refid()
153 g
154 for g in groups
155 if g.get_compounddef()[0].get_id()
/Zephyr-latest/drivers/led_strip/
Dlpd880x.c92 uint8_t r, g, b; in lpd880x_strip_update_rgb() local
101 g = 0x80 | (pixels[i].g >> 1); in lpd880x_strip_update_rgb()
108 *px++ = g; in lpd880x_strip_update_rgb()
Dapa102.c64 uint8_t g = pixels[i].g; in apa102_update_rgb() local
69 *p++ = g; in apa102_update_rgb()
/Zephyr-latest/drivers/flash/
DKconfig.ambiq14 Enables Ambiq flash driver on MRAM (e.g. Apollo4x) or
15 flash (e.g. Apollo3x).
/Zephyr-latest/doc/services/ipc/ipc_service/backends/
Dicbmsg_memory.svg3 <g>
5 <g transform="translate(-0.5 -0.5)">
20 </g>
22 <g transform="translate(-0.5 -0.5)">
37 </g>
39 <g transform="translate(-0.5 -0.5)">
54 </g>
56 <g transform="translate(-0.5 -0.5)">
71 </g>
73 <g transform="translate(-0.5 -0.5)">
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Dicbmsg_message.svg3 <g>
5 <g transform="translate(-0.5 -0.5)">
20 </g>
22 <g transform="translate(-0.5 -0.5)">
37 </g>
39 <g transform="translate(-0.5 -0.5)">
54 </g>
56 <g transform="translate(-0.5 -0.5)">
71 </g>
73 <g transform="translate(-0.5 -0.5)">
[all …]
Dicbmsg_flows.svg3 <g>
5 <g transform="translate(-0.5 -0.5)">
22 </g>
24 <g transform="translate(-0.5 -0.5)">
41 </g>
44 <g transform="translate(-0.5 -0.5)">
61 </g>
64 <g transform="translate(-0.5 -0.5)">
81 </g>
84 <g transform="translate(-0.5 -0.5)">
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/Zephyr-latest/cmake/compiler/host-gcc/
Dtarget.cmake8 set(cplusplus_compiler g++)
10 if(EXISTS g++)
11 set(cplusplus_compiler g++)
/Zephyr-latest/tests/drivers/i2c/i2c_ram/
DREADME.rst10 - Target supporting I2C (with RTIO for the I2C_RTIO test-cases), e.g: mimxrt1010_evk.
11 - External I2C RAM chipset connected to the I2C bus, e.g: Fujitsu's MB85 FeRAM.
/Zephyr-latest/drivers/sensor/bosch/bma280/
DKconfig64 bool "+/-2g"
67 bool "+/-4g"
70 bool "+/-8g"
73 bool "+/-16g"

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