Searched refs:dividers (Results 1 – 2 of 2) sorted by relevance
139 } dividers[] = { in find_suitable_clock() local155 for (uint8_t d = 0; (best_diff != 0) && (d < ARRAY_SIZE(dividers)); ++d) { in find_suitable_clock()157 src_freq / dividers[d].divider_val; in find_suitable_clock()166 best_mck_cfg = dividers[d].divider_enum; in find_suitable_clock()
77 * WORKAROUND: stm32l4-pll-clock does not allow arbitrary PLLP dividers.
