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/Zephyr-latest/tests/drivers/sensor/adltc2990/boards/
Dnative_sim.overlay13 pin-v1-voltage-divider-resistors = <500 1000>;
14 pin-v2-voltage-divider-resistors = <110000 100000>;
15 pin-v3-voltage-divider-resistors = <7000 1000>;
16 pin-v4-voltage-divider-resistors = <500 1000>;
27 pin-v1-voltage-divider-resistors = <0 1>;
28 pin-v2-voltage-divider-resistors = <0 1>;
29 pin-v3-voltage-divider-resistors = <0 1>;
30 pin-v4-voltage-divider-resistors = <0 1>;
39 pin-v1-voltage-divider-resistors = <0 1>;
40 pin-v2-voltage-divider-resistors = <0 1>;
[all …]
/Zephyr-latest/soc/nxp/rw/
Dflexspi_clock_setup.c25 uint32_t divider; in flexspi_clock_set_freq() local
36 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
38 divider = MIN(divider, CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK); in flexspi_clock_set_freq()
46 CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK), (divider + 1)); in flexspi_clock_set_freq()
60 void __ramfunc set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in set_flexspi_clock() argument
65 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1); in set_flexspi_clock()
/Zephyr-latest/soc/nxp/mcx/mcxn/
Dflash_clock_setup.c12 uint8_t divider; in flexspi_clock_set_freq() local
17 divider = ((pll_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
19 divider = MIN(divider, 8); in flexspi_clock_set_freq()
20 SYSCON->FLEXSPICLKDIV = divider; in flexspi_clock_set_freq()
/Zephyr-latest/drivers/clock_control/
Dclock_control_si32_apb.c20 uint32_t divider; member
44 *rate /= config->divider; in clock_control_si32_apb_get_rate()
63 if (config->divider == 1) { in clock_control_si32_apb_init()
65 } else if (config->divider == 2) { in clock_control_si32_apb_init()
76 .divider = DT_PROP(DT_NODELABEL(clk_apb), divider),
Dclock_control_r8a779f0_cpg_mssr.c202 static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a779f0_set_rate_helper() argument
207 if (*divider > 3 && *divider < 7) { in r8a779f0_set_rate_helper()
209 *divider -= 4; in r8a779f0_set_rate_helper()
210 *divider <<= R8A779F0_CLK_SDSRC_DIV_SHIFT; in r8a779f0_set_rate_helper()
217 if (*divider == 2 || *divider == 4) { in r8a779f0_set_rate_helper()
219 *divider >>= 2; in r8a779f0_set_rate_helper()
226 if (!is_power_of_two(*divider) || *divider > 16) { in r8a779f0_set_rate_helper()
230 *divider = (find_lsb_set(*divider) - 1) << R8A779F0_CLK_SD0H_DIV_SHIFT; in r8a779f0_set_rate_helper()
Dclock_control_r8a7795_cpg_mssr.c204 static int r8a7795_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a7795_set_rate_helper() argument
212 if (*divider == 2 || *divider == 4) { in r8a7795_set_rate_helper()
214 *divider >>= 2; in r8a7795_set_rate_helper()
225 if (!is_power_of_two(*divider) || *divider > 16) { in r8a7795_set_rate_helper()
230 *divider = (find_lsb_set(*divider) - 1) << R8A7795_CLK_SDH_DIV_SHIFT; in r8a7795_set_rate_helper()
235 *divider -= 1; in r8a7795_set_rate_helper()
236 if (*divider <= R8A7795_CLK_CANFD_DIV_MASK) { in r8a7795_set_rate_helper()
Dclock_control_renesas_cpg_mssr.c94 uint32_t divider = RCAR_CPG_NONE; in rcar_cpg_get_divider() local
111 divider = data->get_div_helper(reg_val, clk_info->module); in rcar_cpg_get_divider()
114 if (!divider) { in rcar_cpg_get_divider()
118 return divider; in rcar_cpg_get_divider()
123 uint32_t divider = rcar_cpg_get_divider(dev, clk_info); in rcar_cpg_update_out_freq() local
125 if (divider == RCAR_CPG_NONE) { in rcar_cpg_update_out_freq()
129 clk_info->out_freq = clk_info->in_freq / divider; in rcar_cpg_update_out_freq()
267 uint32_t divider; in rcar_cpg_set_rate() local
302 divider = in_freq / u_rate; in rcar_cpg_set_rate()
303 if (divider * u_rate != in_freq) { in rcar_cpg_set_rate()
[all …]
/Zephyr-latest/drivers/pwm/
Dpwm_sam.c30 uint8_t divider; member
38 uint8_t divider = config->divider; in sam_pwm_get_cycles_per_sec() local
41 ((1 << prescaler) * divider); in sam_pwm_get_cycles_per_sec()
101 uint8_t divider = config->divider; in sam_pwm_init() local
116 pwm->PWM_CLK = PWM_CLK_PREA(prescaler) | PWM_CLK_DIVA(divider); in sam_pwm_init()
133 .divider = DT_INST_PROP(inst, divider), \
/Zephyr-latest/soc/nxp/imxrt/imxrt118x/
Dflexspi.c21 uint32_t divider; in flexspi_clock_set_freq() local
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
56 CLOCK_SetRootClockDiv(flexspi_clk, divider); in flexspi_clock_set_freq()
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dflexspi.c21 uint32_t divider; in flexspi_clock_set_freq() local
45 divider = ((root_rate + (rate - 1)) / rate); in flexspi_clock_set_freq()
47 divider = MIN(divider, CCM_CLOCK_ROOT_CONTROL_DIV_MASK); in flexspi_clock_set_freq()
56 CLOCK_SetRootClockDiv(flexspi_clk, divider); in flexspi_clock_set_freq()
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dflexspi.c16 uint8_t divider; in flexspi_clock_set_freq() local
47 divider = ((root_rate + (rate - 1)) / rate) - 1; in flexspi_clock_set_freq()
49 divider = MIN(divider, kCLOCK_FlexspiDivBy8); in flexspi_clock_set_freq()
58 CLOCK_SetDiv(div_sel, divider); in flexspi_clock_set_freq()
/Zephyr-latest/drivers/mdio/
Dmdio_xmc4xxx.c30 uint8_t divider; member
35 {.divider = 8, .reg_val = 2}, {.divider = 13, .reg_val = 3},
36 {.divider = 21, .reg_val = 0}, {.divider = 31, .reg_val = 1},
37 {.divider = 51, .reg_val = 4}, {.divider = 62, .reg_val = 5},
125 uint8_t divider = mdio_clock_divider[i].divider; in mdio_xmc4xxx_set_clock_divider() local
127 uint32_t mdc_clk = eth_mac_clk / divider; in mdio_xmc4xxx_set_clock_divider()
130 LOG_DBG("Using MDC clock divider %d", divider); in mdio_xmc4xxx_set_clock_divider()
Dmdio_nxp_enet_qos.c158 int ret, divider; in nxp_enet_qos_mdio_init() local
173 divider = 2; in nxp_enet_qos_mdio_init()
175 divider = 3; in nxp_enet_qos_mdio_init()
177 divider = 0; in nxp_enet_qos_mdio_init()
179 divider = 1; in nxp_enet_qos_mdio_init()
181 divider = 4; in nxp_enet_qos_mdio_init()
189 ENET_QOS_REG_PREP(MAC_MDIO_ADDRESS, CR, divider); in nxp_enet_qos_mdio_init()
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dflash_clock_setup.c78 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in flexspi_setup_clock() argument
83 (divider - 1))) { in flexspi_setup_clock()
97 CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1); in flexspi_setup_clock()
108 (divider - 1))) { in flexspi_setup_clock()
122 CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1); in flexspi_setup_clock()
/Zephyr-latest/samples/sensor/lps22hh_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/samples/basic/blinky_pwm/boards/
Drpi_pico.overlay7 divider-frac-4 = <15>;
8 divider-int-4 = <255>;
Dxiao_rp2040.overlay11 divider-frac-4 = <15>;
12 divider-int-4 = <255>;
/Zephyr-latest/samples/basic/fade_led/boards/
Dcyw920829m2evk_02.overlay29 divider-type = <CY_SYSCLK_DIV_16_BIT>;
30 divider-sel = <1>;
31 divider-val = <9599>;
/Zephyr-latest/drivers/serial/
Duart_b91.c142 uint16_t *divider, uint8_t *bwpc) in uart_b91_cal_div_and_bwpc() argument
186 *divider = D_int[position_min] - 1; in uart_b91_cal_div_and_bwpc()
189 *divider = D_int[position_max]; in uart_b91_cal_div_and_bwpc()
193 *divider = D_int[position_min] - 1; in uart_b91_cal_div_and_bwpc()
196 *divider = D_int[position_max]; in uart_b91_cal_div_and_bwpc()
201 static void uart_b91_init(volatile struct uart_b91_t *uart, uint16_t divider, in uart_b91_init() argument
205 divider = divider | FLD_UART_CLK_DIV_EN; in uart_b91_init()
207 uart->clk_div = divider; in uart_b91_init()
250 uint16_t divider; in uart_b91_configure() local
285 uart_b91_cal_div_and_bwpc(cfg->baudrate, sys_clk.pclk * 1000 * 1000, &divider, &bwpc); in uart_b91_configure()
[all …]
/Zephyr-latest/soc/nxp/kinetis/k8x/
DKconfig35 int "Freescale K8x core clock divider"
42 int "Freescale K8x bus clock divider"
49 int "Freescale K8x FlexBus clock divider"
56 int "Freescale K8x flash clock divider"
/Zephyr-latest/samples/boards/nordic/battery/
DREADME.rst14 ``voltage-divider`` then the voltage is measured using that divider. An
15 example of a devicetree node describing a voltage divider for battery
22 compatible = "voltage-divider";
30 * If the board does not have a voltage divider and so no ``/vbatt`` node
45 Note that in many cases where there is no voltage divider the digital
66 A Nordic-based board, optionally with a voltage divider specified in its
/Zephyr-latest/drivers/can/
Dcan_sam0.c30 int divider; member
101 *rate = SOC_ATMEL_SAM0_DFLL48_FREQ_HZ / (sam_cfg->divider); in can_sam0_get_core_clock()
104 *rate = SOC_ATMEL_SAM0_OSC48M_FREQ_HZ / (sam_cfg->divider); in can_sam0_get_core_clock()
116 | GCLK_GENCTRL_DIV(cfg->divider) in can_sam0_clock_enable()
121 | GCLK_GENCTRL_DIV(cfg->divider) in can_sam0_clock_enable()
217 .divider = DT_INST_PROP(inst, divider), \
/Zephyr-latest/samples/sensor/fdc2x1x/boards/
Dnrf9160dk_nrf9160.overlay22 fref-divider = <1>;
31 fref-divider = <1>;
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/
Dflash_clock_setup.c79 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in flexspi_setup_clock() argument
84 (divider - 1))) { in flexspi_setup_clock()
98 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1); in flexspi_setup_clock()

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