Searched refs:divclk (Results 1 – 4 of 4) sorted by relevance
1316 for (div = ldev->divclk.min; div <= ldev->divclk.max; div++) { in litex_clk_calc_all_params()1359 div = ldev->divclk.min * lcko->clkout_div.min; in litex_clk_check_rate_range()1364 div = ldev->divclk.max * lcko->clkout_div.max; in litex_clk_check_rate_range()1693 ldev->divclk.min = DIVCLK_DIVIDE_MIN; in litex_clk_dts_global_ranges_read()1694 ldev->divclk.max = DIVCLK_DIVIDE_MAX; in litex_clk_dts_global_ranges_read()1788 .divclk = {DIVCLK_DIVIDE_MIN, DIVCLK_DIVIDE_MAX},
241 struct litex_clk_range divclk; /* divclk_divide_range */ member
380 litex,divclk-divide-min = <1>;381 litex,divclk-divide-max = <107>;
41 …defining values for FPGA-specific configuration (parameters from ``litex,divclk-divide-min`` to ``…
