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/Zephyr-latest/drivers/watchdog/
Dwdt_intel_adsp.h92 uint32_t control; in intel_adsp_wdt_pause() local
94 control = sys_read32(reg_addr); in intel_adsp_wdt_pause()
95 control &= DSPCxWDTCS_STORE; in intel_adsp_wdt_pause()
96 control |= FIELD_PREP(DSPCxWDTCS_PCODE, DSPCxWDTCS_PCODE_VALUE); in intel_adsp_wdt_pause()
97 sys_write32(control, reg_addr); in intel_adsp_wdt_pause()
111 uint32_t control; in intel_adsp_wdt_resume() local
113 control = sys_read32(reg_addr); in intel_adsp_wdt_resume()
114 control &= DSPCxWDTCS_STORE; in intel_adsp_wdt_resume()
115 control |= DSPCxWDTCS_PAUSED; in intel_adsp_wdt_resume()
116 sys_write32(control, reg_addr); in intel_adsp_wdt_resume()
Dwdt_dw.h307 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_enable() local
309 control |= WDT_CR_WDT_EN; in dw_wdt_enable()
310 sys_write32(control, base + WDT_CR); in dw_wdt_enable()
327 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_response_mode_set() local
330 control |= WDT_CR_RMOD; in dw_wdt_response_mode_set()
332 control &= ~WDT_CR_RMOD; in dw_wdt_response_mode_set()
335 sys_write32(control, base + WDT_CR); in dw_wdt_response_mode_set()
346 uint32_t control = sys_read32(base + WDT_CR); in dw_wdt_reset_pulse_length_set() local
348 control &= ~WDT_CR_RPL; in dw_wdt_reset_pulse_length_set()
349 control |= FIELD_PREP(WDT_CR_RPL, pclk_cycles); in dw_wdt_reset_pulse_length_set()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_mchp_mss.c109 uint32_t control; member
129 uint32_t control; in mss_spi_hw_tfsz_set() local
132 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL); in mss_spi_hw_tfsz_set()
133 control &= ~MSS_SPI_CONTROL_CNT_MSK; in mss_spi_hw_tfsz_set()
134 control |= ((len & MSS_SPI_FRAMESUP_LO_BYTES_MSK) << MSS_SPI_CONTROL_CNT_SHF); in mss_spi_hw_tfsz_set()
135 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control); in mss_spi_hw_tfsz_set()
140 uint32_t control; in mss_spi_enable_controller() local
142 control = mss_spi_read(cfg, MSS_SPI_REG_CONTROL); in mss_spi_enable_controller()
143 control |= MSS_SPI_CONTROL_ENABLE; in mss_spi_enable_controller()
144 mss_spi_write(cfg, MSS_SPI_REG_CONTROL, control); in mss_spi_enable_controller()
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Dspi_litex.c52 static int spi_config(const struct device *dev, const struct spi_config *config, uint16_t *control) in spi_config() argument
109 *control = (uint16_t) (SPI_WORD_SIZE_GET(config->operation) in spi_config()
115 litex_write16(*control, dev_config->control_addr); in spi_config()
123 uint16_t control) in spi_litex_send() argument
129 litex_write16(control | BIT(0), dev_config->control_addr); in spi_litex_send()
146 uint16_t control) in spi_litex_xfer() argument
165 spi_litex_send(dev, txd, control); in spi_litex_xfer()
193 uint16_t control = 0; in spi_litex_transceive() local
196 ret = spi_config(dev, config, &control); in spi_litex_transceive()
201 spi_litex_xfer(dev, config, control); in spi_litex_transceive()
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/Zephyr-latest/subsys/bluetooth/audio/
DKconfig.mctl1 # Bluetooth Audio - Media control configuration options
13 bool "Support for media player control"
15 Enables support for control of local and remote media players
16 To enable support for control of a local media player, support for
22 bool "Support for control of local media player"
24 This option enables support for control of a local media player
27 bool "Support for local control of local media player"
31 This option enables support for local application control of local
35 bool "Support for remote control of local media players"
38 This option enables support for remote control of local media
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/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8801.c63 uint8_t new_value, control; in gpio_it8801_configure() local
74 ret = i2c_reg_read_byte_dt(&config->i2c_dev, reg_gpcr, &control); in gpio_it8801_configure()
81 control &= ~(IT8801_GPIODIR | IT8801_GPIOPDE | IT8801_GPIOPUE); in gpio_it8801_configure()
101 control |= IT8801_GPIODIR; in gpio_it8801_configure()
104 control |= IT8801_GPIOIOT_OD; in gpio_it8801_configure()
106 control &= ~IT8801_GPIOIOT_OD; in gpio_it8801_configure()
110 control &= ~IT8801_GPIODIR; in gpio_it8801_configure()
115 control = (control | IT8801_GPIOPUE) & ~IT8801_GPIOPDE; in gpio_it8801_configure()
117 control = (control | IT8801_GPIOPDE) & ~IT8801_GPIOPUE; in gpio_it8801_configure()
120 control &= ~(IT8801_GPIOPUE | IT8801_GPIOPDE); in gpio_it8801_configure()
[all …]
/Zephyr-latest/drivers/sensor/s11059/
Ds11059.c123 static int s11059_control_write(const struct device *dev, uint8_t control) in s11059_control_write() argument
126 const uint8_t opcode[] = {S11059_REG_ADDR_CONTROL, control}; in s11059_control_write()
143 uint8_t control; in s11059_start_measurement() local
147 rc = i2c_reg_read_byte_dt(&cfg->bus, S11059_REG_ADDR_CONTROL, &control); in s11059_start_measurement()
154 WRITE_BIT(control, S11059_CONTROL_ADC_RESET, 1); in s11059_start_measurement()
155 WRITE_BIT(control, S11059_CONTROL_STADBY, 0); in s11059_start_measurement()
156 rc = s11059_control_write(dev, control); in s11059_start_measurement()
163 WRITE_BIT(control, S11059_CONTROL_ADC_RESET, 0); in s11059_start_measurement()
164 rc = s11059_control_write(dev, control); in s11059_start_measurement()
202 uint8_t control; in s11059_sample_fetch() local
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/Zephyr-latest/boards/nordic/nrf9160dk/
Dnrf9160dk_nrf52840.dts52 board-control {
55 control-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
65 control-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>,
72 control-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
78 control-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
84 control-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
90 control-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
96 control-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
102 control-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
108 control-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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Dnrf9160dk_nrf52840_0_14_0.overlay8 board-control {
11 control-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
17 control-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
23 control-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
45 control-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
/Zephyr-latest/dts/riscv/sifive/
Driscv32-fe310.dtsi54 reg-names = "control";
61 reg-names = "control";
72 reg-names = "control";
97 reg-names = "control";
115 reg-names = "control";
138 reg-names = "control", "mem";
143 reg-names = "control";
150 reg-names = "control";
160 reg-names = "control";
170 reg-names = "control";
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/Zephyr-latest/drivers/ipm/
Dipm_esp32.c51 struct esp32_ipm_control *control; member
75 while (!atomic_cas(&dev_data->control->lock, ESP32_IPM_LOCK_FREE_VAL, in esp32_ipm_isr()
90 dev_data->control->dest_cpu_msg_id[core_id], in esp32_ipm_isr()
95 atomic_set(&dev_data->control->lock, ESP32_IPM_LOCK_FREE_VAL); in esp32_ipm_isr()
121 while (!atomic_cas(&dev_data->control->lock, in esp32_ipm_send()
139 dev_data->control->dest_cpu_msg_id[dev_data->other_core_id] = (uint16_t)(id & 0xFFFF); in esp32_ipm_send()
144 atomic_set(&dev_data->control->lock, ESP32_IPM_LOCK_FREE_VAL); in esp32_ipm_send()
154 atomic_set(&dev_data->control->lock, ESP32_IPM_LOCK_FREE_VAL); in esp32_ipm_send()
221 LOG_DBG("Address of IPM control structure: %p", (void *)data->control); in esp32_ipm_init()
238 atomic_set(&data->control->lock, ESP32_IPM_LOCK_FREE_VAL); in esp32_ipm_init()
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/Zephyr-latest/drivers/mbox/
Dmbox_esp32.c52 struct esp32_mbox_control *control; member
77 while (!atomic_cas(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL, in esp32_mbox_isr()
93 atomic_set(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL); in esp32_mbox_isr()
111 while (!atomic_cas(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL, in esp32_mbox_send()
117 dev_data->control->dest_cpu_msg_id[dev_data->other_core_id] = (uint16_t)(channel & 0xFFFF); in esp32_mbox_send()
121 atomic_set(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL); in esp32_mbox_send()
130 atomic_set(&dev_data->control->lock, ESP32_MBOX_LOCK_FREE_VAL); in esp32_mbox_send()
205 LOG_DBG("Address of MBOX control structure: %p", data->control); in esp32_mbox_init()
214 atomic_set(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL); in esp32_mbox_init()
226 while (!atomic_cas(&data->control->lock, ESP32_MBOX_LOCK_FREE_VAL, in esp32_mbox_init()
[all …]
/Zephyr-latest/drivers/clock_control/
DKconfig.si326 bool "SI32 PLL clock control"
11 bool "SI32 AHB clock control"
16 bool "SI32 APB clock control"
DKconfig.ifx_cat11 # Infineon CAT1 clock control driver
8 bool "Infineon CAT1 clock control driver"
12 This option enables the clock control driver for Infineon CAT1 family.
DKconfig.litex1 # LiteX SoC Builder clock control driver
7 bool "LiteX MMCM clock control"
11 This option enables LiteX clock control driver.
DKconfig.silabs5 bool "Silicon Labs Series 2+ clock control driver"
9 Enable Silicon Labs Series 2+ Clock Management Unit clock control driver.
DKconfig.lpc11u6x1 # LPC11U6X MCU clock control driver config
7 bool "LPC11U6X Reset and clock control"
12 Enable driver for reset and clock control used in
DKconfig.ambiq9 bool "AMBIQ clock control driver"
14 Enable driver for Ambiq clock control.
DKconfig.cavs1 # Intel cAVS clock control driver
7 bool "Intel CAVS clock control"
/Zephyr-latest/boards/infineon/cy8cproto_062_4343w/
Dcy8cproto_062_4343w-pinctrl.dtsi6 /* Configure pin control bias mode for uart2 pins */
23 /* Configure pin control bias mode for uart5 pins */
32 /* Configure pin control bias mode for i2c3 pins */
44 /* Configure pin control bias mode for SDIO */
/Zephyr-latest/doc/connectivity/bluetooth/shell/audio/
Dmcp.rst4 This document describes how to run the media control functionality,
7 The media control server consists of to parts. There is a media
9 media control service (mcs) that serves as a GATT-based interface to
10 the player. The media control client consists of one part, the GATT
13 The media control server may include an object transfer service (ots)
14 and the media control client may include an object transfer client
18 The media control server and client both implement the Generic Media
61 player by writing to the *media control point*. There is also a
62 *search control point* that allows to search for groups and tracks
66 Finally, the *content control ID* is used to associate the media
[all …]
/Zephyr-latest/doc/hardware/peripherals/
Dtcpc.rst13 * VBUS and VCONN control `USB Type-C <usb-type-c-specification_>`_:
14 The TCPC may provide a Source device, the mechanism to control VBUS sourcing,
15 and a Sink device, the mechanism to control VBUS sinking. A similar mechanism
16 is provided for the control of VCONN.
18 * CC control and sensing:
34 device driver that's used to communicate with and control the TCPC device.
/Zephyr-latest/tests/subsys/usb/uac2/
Dapp.overlay20 frequency-control = "host-programmable";
35 mute-control = "host-programmable";
36 automatic-gain-control =
66 mute-control = "host-programmable";
67 automatic-gain-control =
107 frequency-control = "host-programmable";
/Zephyr-latest/subsys/mgmt/osdp/src/
Dosdp_phy.c24 uint8_t control; member
78 if (pkt->control & PKT_CONTROL_SCB) { in osdp_phy_packet_get_data_offset()
93 if (pkt->control & PKT_CONTROL_SCB) { in osdp_phy_packet_get_smb()
142 pkt->control = osdp_phy_get_seq_number(pd, is_cp_mode(pd)); in osdp_phy_packet_init()
143 pkt->control |= PKT_CONTROL_CRC; in osdp_phy_packet_init()
146 pkt->control |= PKT_CONTROL_SCB; in osdp_phy_packet_init()
150 pkt->control |= PKT_CONTROL_SCB; in osdp_phy_packet_init()
196 if (sc_is_active(pd) && (pkt->control & PKT_CONTROL_SCB) && pkt->data[1] >= SCS_15) { in osdp_phy_packet_finalize()
308 if (pkt->control & PKT_CONTROL_CRC) { in osdp_phy_check_packet()
342 comp = pkt->control & PKT_CONTROL_SQN; in osdp_phy_check_packet()
[all …]
/Zephyr-latest/drivers/dma/
Ddma_mchp_xec.c91 volatile uint32_t control; member
123 uint32_t control; member
198 chregs->control = 0; in xec_dma_chan_clr()
202 chregs->control = 0; in xec_dma_chan_clr()
426 chdata->control = ctrl; in dma_xec_configure()
436 chregs->control = ctrl; in dma_xec_configure()
466 if (chregs->control & BIT(XEC_DMA_CHAN_CTRL_BUSY_POS)) { in dma_xec_reload()
470 ctrl = chregs->control & ~(BIT(XEC_DMA_CHAN_CTRL_HWFL_RUN_POS) in dma_xec_reload()
473 chregs->control = 0; in dma_xec_reload()
491 chregs->control = ctrl; in dma_xec_reload()
[all …]

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