Searched refs:clr (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-latest/arch/sparc/core/ |
| D | reset_trap.S | 45 clr %fp
46 clr %i7
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_bcm2711.c | 147 uint64_t set, clr; in gpio_bcm2711_port_set_masked_raw() local
156 clr = regval ^ regmask; in gpio_bcm2711_port_set_masked_raw()
159 sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0)); in gpio_bcm2711_port_set_masked_raw()
161 sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1)); in gpio_bcm2711_port_set_masked_raw()
199 uint64_t set, clr; in gpio_bcm2711_port_toggle_bits() local
207 clr = regval & regmask; in gpio_bcm2711_port_toggle_bits()
210 sys_write32(FROM_U64(clr, 0), GPCLR(data->base, 0)); in gpio_bcm2711_port_toggle_bits()
212 sys_write32(FROM_U64(clr, 1), GPCLR(data->base, 1)); in gpio_bcm2711_port_toggle_bits()
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| D | gpio_lpc11u6x.c | 51 volatile uint32_t clr[3]; member
172 gpio_regs->clr[port_num] |= BIT(pin); in gpio_lpc11u6x_pin_configure()
241 gpio_regs->clr[config->port_num] = pins; in gpio_lpc11u6x_port_clear_bits_raw()
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| D | gpio_renesas_ra.c | 133 const uint16_t clr = (~value) & mask; in port_write() local
135 reg_write(dev, PCNTR3_OFFSET, (clr << PCNTR3_PORR0_OFFSET) | set << PCNTR3_POSR0_OFFSET); in port_write()
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| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | cpuclk.c | 45 uint32_t clr; member
113 MTK_CLK_GEN.clk_cfg[clk].clr = (0xf << shift); in setclk()
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| /Zephyr-latest/subsys/bluetooth/mesh/ |
| D | rpl.c | 348 bool clr; in bt_mesh_rpl_pending_store() local
361 clr = atomic_test_and_clear_bit(rpl_flags, PENDING_CLEAR); in bt_mesh_rpl_pending_store()
371 if (clr) { in bt_mesh_rpl_pending_store()
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| D | solicitation.c | 429 bool clr; in bt_mesh_srpl_pending_store() local
431 clr = atomic_cas(&clear, 1, 0); in bt_mesh_srpl_pending_store()
436 if (clr) { in bt_mesh_srpl_pending_store()
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